Summary
Overview
Work History
Education
Skills
Timeline
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Valentina Turaka

Hyderabad

Summary

Having experience of 5.1 years in STA at block level and Top level. Good knowledge on STA concepts, VLSI basics and good understanding of digital concepts. Experience in advanced technology nodes: 16nm, 14nm and 10nm. Experience in creating and verifying timing ECO’s. Experience in handling critical timing paths to identify key issues and fixes. Experience in working with different teams to understand, debug and resolve the issues related to timing fixes. Understanding of Crosstalk. Basic knowledge of TCL. Basic knowledge of OCV/AOCV concepts

Overview

5
5
years of professional experience
2003
2003
years of post-secondary education

Work History

Block level STA

RENESAS
07.2024 - Current
  • Conducted timing signoff for post-layout designs, ensuring all critical paths met timing constraints across various corner cases and process variations.
  • Identified timing violations and provided solutions through optimization techniques, such as adjusting clock constraints, retiming, and introducing buffer insertions.
  • Collaborated with design teams to define and refine clocking architectures and timing constraints.
  • Automated STA flows and scripts to improve the efficiency and accuracy of the analysis process.
  • Worked closely with the Physical Design team to resolve timing issues related to layout, including parasitic extraction and back-annotation.
  • Documented and reported STA results to senior management and design teams for further analysis and resolution.

LANCESOFT ENGINEERING PVT.LTD
05.2020 - Current

Block level STA

RENESAS
12.2023 - 06.2024
  • Automating parts of the STA process, like scripting for common fixes or violations, to improve efficiency.
  • Use of design methodologies such as clock-domain isolation, multi-cycle path definition, and retiming to help manage complex designs and mitigate STA challenges.
  • Coordination between the design, verification, and physical implementation teams to ensure that timing constraints are met, and issues are resolved promptly.
  • Identifying critical paths that are causing timing violations.
  • Identifying and resolving timing violations, such as setup and hold violations, recovery and removal violations.

Block level STA

NXP
06.2022 - 11.2023
  • Achieving Timing Closure by identifying and resolving timing violations, such as setup and hold violations, recovery and removal violations.
  • Identifying critical paths that are causing timing violations.
  • Analyzed timing analysis of interpreting timing reports, effects of clock skew on timing and fixing timing violations.
  • Understanding of Crosstalk analysis.
  • Good understanding of OCV, AOCV, CRPR.

Block level STA

NVIDIA
03.2021 - 05.2022
  • Top level STA using Prime Time signoff tool.
  • Using DMSA flow for ECO generation.
  • Preparing the manual ECOs for unfixed paths by DMSA flow.
  • Fixing the timing and DRV.

Block level STA

NVIDIA
05.2020 - 02.2021
  • Dealing with Timing Paths and Constraints.
  • Handling Process, Voltage, and Temperature (PVT) Variations.
  • Preparing the manual ECOs for unfixed paths by DMSA flow.

Education

B-Tech - Electrical and Electronics Engineering

D M S S V H College of Engineering

M-Tech - Electrical and Electronics Engineering

NIST

Skills

  • Primetime
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Timeline

Block level STA

RENESAS
07.2024 - Current

Block level STA

RENESAS
12.2023 - 06.2024

Block level STA

NXP
06.2022 - 11.2023

Block level STA

NVIDIA
03.2021 - 05.2022

LANCESOFT ENGINEERING PVT.LTD
05.2020 - Current

Block level STA

NVIDIA
05.2020 - 02.2021

M-Tech - Electrical and Electronics Engineering

NIST

B-Tech - Electrical and Electronics Engineering

D M S S V H College of Engineering

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Valentina Turaka