Vamsi Krishna Polagani

I am a 6+ years of experienced Analog Layout Engineer with a proven track record in designing and implementing complex analog and mixed-signal layouts. Possessing a deep understanding of semiconductor processes and layout techniques, with a focus on optimizing performance, area, and power metrics. Skilled in CAD tools such as Cadence Virtuoso, Mentor Graphics, and Synopsys IC Compiler for layout design, verification, and physical implementation.

• ADC: DAO_SPINE_REGISTERS_TOP (COHERENT OPTICS PRODUCT), TSMC4ff, Cadence Virtuoso-EXL, Calibre, Worked on SAR-ADC in which DAO_SPINE_REGISTERS_TOP block. Worked on SPINE_REGISTERS from scratch level from initial floorplan, routing, verification (DRC/LVS) of blocks from bottom-level to top-level. Taken care of level shifters and register block floorplan and routings as per the top -level requirement (DAO_SPINE_REGISTERS_LEFT, RIGHT, DLL2, DLL, RVDD09ARBnDL). Planned the routing sequence oCTRL14_15, ID09_REG9
• R/W, XRST, ADDR
• Signals as per next level requirement. Worked on power routing of DAO_SPINE_REGISTERS_TOP level as per top-level power grid with strong power/ground connections. Decaps are added on power and ground to bypass the unwanted spike or noise in power. Cleaned all PV checks that required upto top-level.
• ADC: DAO_FE_TOP (COHERENT OPTICS PRODUCT), TSMC4ff, Cadence Virtuoso-EXL, Calibre, Worked on sub-blocks DAO_FE_SIGPATH_WBIAS level of design updates and cleaned verification (DRC, LVS, ERC & ANT). Worked on critical design improvements DAO_FE_D0_BIAS, D1, D2 and SAMP_BIAS blocks. Taken care of CLK, bias signals while routing by providing shielding. Fixed lakhs of delta violation errors and FB
• Errors in DRC. Worked on level shifters updates i.e adding new level-shifters floorplan, routing and verification as per design requirement. Taken care of signals that are going to next level as per top-level requirement. Cleaned all DRC errors which includes the chip level density errors & EMIR issues and all signoff checks.
• DDR_PLLS:6.4GHZ, TSMC3nm, TSMC4nm, TSMC5nm, TSMC6nm, TSMC7nm, SS7hpp, SMIC12sfe, Synopsys Custom compiler, IC-Validator, Worked on various DRR_PLLs: DDR54, DDR43, HBM3, LPDDR54, LPDDR5XM, HDMI. Worked on initial floorplan, routing and verification (DRC/LVS) of bandgap_cp, sup_pgate_vp_switch, upll_vco_core_lp blocks in ddr_module level & DDR4_PLL. Taken care of critical signals like clk, bias
• & vref signals with shielding & power planning. Understand and cleaned the FB1AN
• Errors coming in top-level w.r.t prboundary. Clean all PV checks that required upto top-level with fills & fixed EMIR issues. Understood and fixed the ESD, density &P2P related issues coming in CHIP_LEVEL from PLL. Ensure to clean the checks like VDRC, methodology, SNPS, PERC_CNOD, PERC_P2P checks before release the data base to DI team (digital team). Worked on 4 types of macros DDRPHY, PHY, HBM3, LPDDR54.
• XSR: MPLLB_LC_OSC (128GHZ SERDES), TSMC6nm, Custom compiler, IC-Validator, Worked on floorplan, routing, verification, EMIR sims for entire block. Taken care of symmetricity for clkm/clkp signals to maintain equal parasitic. Taken care of density issues on inductor with manual filling and clean DRC. Strong connection is given for clkm/clkp with AP metal which connected to VCO in next level. Design improvements are done as per designer suggestions to meet the frequency from 16GHz to 14GHz.
• XSR: MPLLB_TOP (128GHZ SERDES), TSMC6nm, Custom compiler, IC-Validator, Worked on floorplan, routing & verification. Taken care of Power routing with less IR. Taken care of clk_left & clk_right with less R &C. Worked on EMIR fixes.
• STANDARD CELLS, PLL_VREG_DIG1, CML_LATCH, GF14nm, Virtuoso -L&XL Editor, Calibre, Understood the finfet basic layers, Double patterning techniques and DRC rules. Worked on floorplan, routing and verification for the pll_vref_dig18, cml_latch. Taken care of the RX fin alignment, Double patterning DRC rules for metal layers. Taken care of placement of each divider stage & Clock routing.
• TX_VGEN, GF 28nm, Virtuoso -L&XL Editor, PVS, Worked on the floorplan, routing, power planning & verification. Taken care of power rating of parallel shut block.
• PLL (PHASE LOCKED LOOP):6GHZ, GPDK45nm, Virtuoso -L&XL Editor, PVS, I was involved in layout generation of VCO from Schematic, Floor Planning, Power Management and Cleared DRC and LVS. Matching the Mismatches to meet the same Delay, Placement of Dummies, taking more care on Latch-up Issues, Antenna Effect. Electron Migration and Providing Shielding for Critical Nets.
• OP-AMP & DAC, GPDK45nm, Virtuoso -L&XL Editor, PVS, Worked on Floor plan, Routing and Power planning and Cleared DRC and LVS. Resistors Matching, Matching the Mismatches to meet the Same Delay, Placement of Dummies, taking care on Latch-up issues, Antenna Effect, Electron Migration.
• STANDARD CELLS, TSMC130nm, Worked on designing standard cells like INV, AND, OR, NAND, NOR, MUX and DFF. To draw in Minimum Width using Single Metal, Optimizing the Cell and maintaining Cell Height in terms of Metal2 Pitches, following Half DRC rules. Maintained continuous diffusion wherever possible to minimize the area & for power efficiency.