Summary
Overview
Work History
Education
Skills
Certification
College Projects
Accomplishments
Affiliations
Languages
References
Timeline
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Ved Prakash Pandey

Ved Prakash Pandey

Jaunpur, Uttar Pradesh

Summary

My goal is to become associated with a company where I can utilize my skills, gain further experience, and enhance the company’s productivity and reputation.

Overview

4
4
years of professional experience
1
1
Certification

Work History

Senior Design Engineer

NXP Semiconductor
Noida
06.2022 - Current
  • Worked on ASIL D interconnect verification (complete path between actual master and slave) in a BFM-based environment. (2 projects: full ownership + 1 partial ownership)
  • End to End parity verif
  • Memory map/reserved space verification automation using python.
  • Taken care of 3 freshers/intern ramp up for SoC verification.
  • Partially worked on debug & trace verif, tester pattern verif, low power clock gating verif
  • recently worked on few corner cases around soft reset domain

Intern, Auto SoC Verif Team

ST MICROELECTRONICS
Greater Noida, UP
05.2021 - 04.2022
  • CRC IP understanding & functional verification at SoC.
  • Verification of xml files having register information of IPs using C based auto generated register test cases at SoC level.
  • Written a script in Bash to ensure each regression session has approximately equal number of tests.
  • IRIS: Creating Library Management System with STM32 Nucleo board, NFC reader, tag, HC-05 & Android platform.(not completed)

Education

Master of Technology - VLSI & Embedded System

IIT Patna
05-2022

Bachelor of Technology - Electrical Engineering

MMMUT
Gorakhpur
04.2018

Intermediate - Physics, Chemistry, Math

St Atulanand Convent School
Varanasi
04.2013

High School - Science, Math

MDJV
Jaunpur
04.2011

Skills

    1 Tools:

  • Cadence Xcelium/SimVision
  • Synopsys Verdi
  • Cadence VManager
  • 2 Protocols:

  • Sky blue line protocol
  • AMBA : APB, AHB, AXI

    3 Language:

  • SV/UVM
  • Verilog
  • Python
  • Bash
  • 4 Good command of gvim and Linux

Certification

  • GATE 2020, 98.77 percentile
  • GATE 2019, 98.22 percentile

College Projects

5-stage pipeline processor in Verilog

Full custom design of an inverter in a 180 nm technology library

Water level indicator using Arduino on a self-developed Android app

Accomplishments

  • Got NXP's highest award, the SPOT award, this year
  • Previous years got 1 winning start here award, 2 cheers for peers award

Affiliations

  • Used to play badminton, table tennis
  • Matchstick crafting

Languages

Hindi
First Language
English
Advanced (C1)
C1

References

References available upon request.

Timeline

Senior Design Engineer

NXP Semiconductor
06.2022 - Current

Intern, Auto SoC Verif Team

ST MICROELECTRONICS
05.2021 - 04.2022

Master of Technology - VLSI & Embedded System

IIT Patna

Bachelor of Technology - Electrical Engineering

MMMUT

Intermediate - Physics, Chemistry, Math

St Atulanand Convent School

High School - Science, Math

MDJV
Ved Prakash Pandey