Traffic Signal Controller Using System Verilog
Mini Project – Computer-Aided Digital Design - Designed a Mealy FSM to manage traffic
Vedant S Kailas
BANGALORE
Summary
Electronics and Communication Engineering student with expertise in digital systems, embedded technology, and HDL programming. Proficient in Verilog/SystemVerilog, circuit design, and microprocessor systems. Passionate about VLSI and quantum computing, consistently seeking innovative solutions to complex challenges. Committed to continuous learning and practical application of advanced technologies.
Work History
Prime Factorization Using RISC-V
Developed an algorithm to compute the prime factors of a number using RISC-V architecture
Smart Billing and Inventory System Using Python
Created a user-friendly Python-based application for grocery billing and inventory tracking
Education
BTech Electronics And Communications CGPA 6.51 -
PES University
Bangalore01-2026
CBSE 12th Standard 78.2% -
Delhi Public School
Bangalore01-2022
CBSE 10th Standard 85.6% -
Kensri School
Bangalore01-2020
Skills
- Programming languages: Python and C
- Hardware description languages: Verilog and SystemVerilog
- Software tools: MATLAB, Simulink
- Domains: RISC-V architecture, Machine Learning, Microprocessors, VLSI, and Quantum Computing
- Soft skills: Problem Solving, Team collaboration
Timeline
Traffic Signal Controller Using System Verilog
Mini Project – Computer-Aided Digital Design - Designed a Mealy FSM to manage traffic
Prime Factorization Using RISC-V
Developed an algorithm to compute the prime factors of a number using RISC-V architecture
Smart Billing and Inventory System Using Python
Created a user-friendly Python-based application for grocery billing and inventory tracking
BTech Electronics And Communications CGPA 6.51 -
PES University
CBSE 12th Standard 78.2% -
Delhi Public School
CBSE 10th Standard 85.6% -
Kensri School
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