VEERANJANEYULU MENDRU
ANALOG VLSI CIRCUIT DESIGNER
Bengaluru
Summary
I possess 11+ years of experience in Analog VLSI Circuit Design related to clocking & bias circuitry for high speed SERDES Design across advanced technology nodes. I am committed to leveraging my skills in the VLSI field to drive technological enhancements
Overview
17
17
years of professional experience
Work History
Principal Design Engineer
CADENCE DESIGN SYSTEMS INDIA PVT LTD
12.2014 - Current
- Designed and led a ring-based 4th-order dual control path PLL with less than 1 ps RJ for multi-protocol support for SerDes applications, with a maximum output frequency of 14.45 GHz.
- Designed a dual control voltage current steering ring oscillator for the frequency range of 8.11 GHz to 14.45 GHz.
- Designed a Phase Frequency Detector (PFD) and an analog-based single-ended charge pump with reduced clock feed-through onto control lines.
- Designed a Delta-Sigma Based Frac-N Divider and developed the Frac-N Divider architecture to improve power and area for the maximum operating frequency of 16 GHz.
- Designed a programmable 'Gm' block, which is used in the PLL.
- Designed analog circuitry for the calibration of transmitter, receiver termination resistors, and bias current generation resistor.
- Designed analog circuitry for JTAG boundary scan (BScan) implementation for high input swings.
- Designed a latch-based oscillator to generate a 500 MHz clock.
- Designed receiver sub-blocks (LSFSRX_DIFFAMP, LSFSRX_SERX, and Clipper) for USB 2.0 protocol application.
- Designed a Low Dropout (LDO) regulator with output voltage programmability, and to support a load current of up to 16 mA.
- Designed a self-biased, high-accuracy bandgap voltage to support regulators and bias generators.
- Designed to generate process- and temperature-dependent constant bias current sources for other sub-blocks in the IP.
- Design experience in designing circuits for reliability, aging, and EM/IR analysis.
Design Engineer
Asarva Chips & Technologies
04.2014 - 11.2014
- Designed a transceiver RF DPDT switch for the frequency band of 57-66 GHz.
- Designed a 5-bit variable phase shifter for the frequency band of 57-66 GHz, which is a key building block in beam-forming applications.
Assistant Professor
Jaya Prakash Narayan College of Engineering
08.2008 - 04.2011
- Taught Signals and Systems, control systems, electromagnetic theory, and electronic circuit analysis subjects.
- Served as the IEEE Student Branch Counselor at Jaya Prakash Narayan College of Engineering for the period 2009-2011.
- Organized a workshop on "Mathematical Perspectives in Signals & Systems" at Jaya Prakash Narayan College of Engineering.
Education
Master of Technology - Microelectronics & VLSI Design
04.2001 -
Bachelor of Technology - Electronics & Comminication Engineering
04.2001 -
Skills
Circuit Design
Timeline
Principal Design Engineer - CADENCE DESIGN SYSTEMS INDIA PVT LTD
12.2014 - Current
Design Engineer - Asarva Chips & Technologies
04.2014 - 11.2014
Assistant Professor - Jaya Prakash Narayan College of Engineering
08.2008 - 04.2011
Indian Institute of Technology - Master of Technology, Microelectronics & VLSI Design
04.2001 -
Jaya Prakash Narayan College of Engineering - Bachelor of Technology, Electronics & Comminication Engineering
04.2001 -