Summary
Overview
Work History
Education
Skills
Accomplishments
Languages
Timeline
Generic

Venkata Kranthi Kiran Cherukuri

Bengaluru

Summary

  • Accomplished Senior Staff Engineer with a proven track record at Qualcomm. Spearheaded over 50+ complex tape-outs, Strengths include leadership, problem-solving and innovative design work. Have significantly contributed to previous organizations by streamlining processes, improving functionality and reducing costs. Known for ability to lead teams effectively and deliver high-quality results.

Overview

9
9
years of professional experience

Work History

Senior Staff Engineer

Qualcomm
Bengaluru
03.2021 - Current
  • Project Leadership: Led over 80+ complex tape-outs, ensuring successful project completion in multiple nodes (TSMC 3nm and 4nm nodes) and have worked on 5nm, 7nm, and 10nm as a Mask Design Engineer, providing critical early PV feedback and supporting full chip verification.
  • Guidance and Collaboration: Provided guidance to the Physical Design (PD) team on floorplan issues, placement of physical IPs, and router-related feedback.
  • Debugging and Issue Resolution: Expertly debugged and addressed DRC, ANTENNA, SOFTCHECK, ERC, and LVS checks, as well as other PV checks at various project stages, aiding the PD team in floor planning, routing, and tape-out stages for smoother PV convergence for core blocks.
  • PV Issue Management: As a lead, closed all PV issues for all HMs in the project and delivered them to SOC for all runs. Drove the team to close all pending ECOs/PDNs, along with other PV checks.
  • DRC Closure: Played a pivotal role in multiple programs by handling complex HMs’ DRC closure without impacting timing and PDN.
  • ECO Implementation: Successfully executed manual ECO implementations across multiple projects, resulting in improved project timelines and reduced errors.
  • PV Checks: Ensured all PV checks were meticulously followed and completed.
  • Training and Collaboration: Conducted basic PV training across all domains to ensure better convergence, enhancing team knowledge and collaboration.
  • Cross-Functional Collaboration: Collaborated with cross-functional teams to identify and resolve PV-related issues, improving overall product quality.
  • Advanced PV Tools: Utilized advanced PV tools and techniques to enhance the accuracy and reliability of validation results.
  • Custom Routing: Delivered custom routing for critical nets from PLLs (3 GHz max frequency) and the temperature sensor, carefully balancing the RC among those routes.
  • PDN Robustness: Worked with the PDN team to complete a custom RDL by implementing a Comb structure routing, significantly enhancing PDN robustness. Enabled Innovus-based void filling for top layers, further improving PDN robustness.
  • Track-Based Utilization: Enabled and analyzed track-based utilization (QUA) for multiple projects, providing feedback to the PD team for better area utilization for upcoming programs, leading to a more effective use of edges.
  • ZeroDRC Methodology: Worked on the ZeroDRC Methodology to ensure that the majority of PV checks were clean at the HM level by implementing correct and constructive methods in collaboration with CAD support.
  • Metal Density Optimization: Developed a density script using track-based metal fill, saving 50% of turnaround time, while ensuring no impact on STA/PDN.

Lead Engineer

Qualcomm
Bengaluru
08.2018 - 04.2021
  • Engaged in cutting-edge Physical Verification (PV) activities for TSMC’s 4nm nodes, with experience in 5nm, 7nm, and 10nm nodes.
  • Provided critical early PV feedback and supported full chip verification and IP verification.
  • Debugged and addressed DRC, ANTENNA, SOFTCHECK, ERC, and LVS checks, as well as other PV checks at different project stages.
  • Assisted the Physical Design team during Floor Plan, Routing, and tape-out stages to ensure smoother PV convergence for core blocks.
  • Led the closure of all PV issues for all Hard Macros (HMs) in the project, delivering them to SOC for all runs.
  • Directed the team to close all pending ECOs/PDNs and other PV checks.
  • Planned resource allocation and made necessary decisions to meet tight timelines.
  • Handled antenna and density checks at the full chip level.
  • Involved in floor planning, routing, and sign-off activities for block-level implementation.
  • Developed skills in understanding floorplan challenges and reducing congestion hot spots with minimal impact on timing convergence.

Senior Physical Verification Engineer

Qualcomm
Bengaluru
02.2016 - 03.2018
  • In Qualcomm through Mirafra Technologies in the CPU/GPU cores team, taped out multiple projects in technology nodes like 14nm, 20nm, and 28nm (SAMSUNG/TSMC foundries) as a Physical Verification Engineer.
  • Debugging and addressing DRC, ERC, LVS checks, soft checks, and other PV checks at different stages of the project helps the Physical Design team at the floor plan, routing, and tape-out stages for smoother PV convergence for core blocks.
  • Achieved experience in handling complex Modem/Tiles/Multimedia/CPU cores, hard macros, and managing/training team members.
  • Provided technical support to other departments in resolving complex convergence-related issues.
  • I worked as a PD engineer on a couple of projects with the Multimedia team on floorplan activities for the wrapper level, and I delivered on time with high quality.
  • I have done pin placement, along with macro placement, by taking care of all PV hotspots by identifying them at early stages.
  • Identified opportunities for improving efficiency in the physical verification process through automation or other means by enabling correctness through constructive methods.

Education

M.Tech VLSI Design - Electronics

Amrita Vishwa Vidyapeetham
Coimbatore
06-2006

Skills

EDA Tools:

  • Synopsys ICCompiler I/II
  • IC Validator
  • Caliber
  • Virtuoso
  • Innovus

Programming Language:

SHELL,PERL,SKILL

Accomplishments

  • Received Appreciations and Awards in Wipro Technologies in meeting the Strict deadlines by handling complex Hard Macro's.
  • Received appreciations from Management for being a Good Mentor for new Joiners.
  • Received Qualstar award for multiple projects for delivering on-time with high quality.
  • Received “Impact Award” from the VP for handling complex PDN-aware net fixes and uplifting frequency by 50 MHz to meet Fmax Target.
  • Wrote couple of QBuzz papers on PDN Robustness and PV Techniques for High-Performance CPU’s
  • Received the ‘Impact Award’ for delivering a complex project with two-week pull-in BTO schedule.

Languages

English
First Language
English
Proficient (C2)
C2
Telugu
Intermediate (B1)
B1
Kannada
Proficient (C2)
C2
Hindi
Proficient (C2)
C2
Tamil
Elementary (A2)
A2

Timeline

Senior Staff Engineer

Qualcomm
03.2021 - Current

Lead Engineer

Qualcomm
08.2018 - 04.2021

Senior Physical Verification Engineer

Qualcomm
02.2016 - 03.2018

M.Tech VLSI Design - Electronics

Amrita Vishwa Vidyapeetham

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Venkata Kranthi Kiran Cherukuri