VENKATA RAYUDU KUPPALA

Dynamic Analog Layout Engineer with vast expertise in advanced TSMC process nodes like 2nm, 3nm, 5nm etc.. consistently delivering high-quality projects and enhancing technical capabilities. Excels in design rule checking and leverages strong collaboration skills alongside proficiency in Cadence Virtuoso tools to drive successful outcomes.

• 7.8 years of hands-on experience in Analog Layout Design, working across advanced technology nodes: TSMC (2nm, 3nm, 5nm, 6nm, 12nm, 16nm, 45nm, 90nm) and Intel (7nm, 22nm).
• Proven expertise in layout design of complex analog blocks, including ADCs, comparators, decoders, current mirrors, differential amplifiers, and operational amplifiers.
• Strong knowledge in Layout Design, Floor Planning, Routing, and Physical Verification, with proficiency in checks such as DRC, LVS, ERC, MRC, Antenna, Soft Checks, CNOD, LEF creation, Gated Diff Area, and Density verification.
• Skilled in identifying and resolving chip failure mechanisms including EM & IR drop issues, shielding challenges, antenna effects, latch-up prevention, and transistor matching techniques.
• Adept at meeting aggressive tape-out schedules, demonstrating high productivity in closing violations and ensuring sign-off quality.
• Recognized for team collaboration and ability to take ownership in delivering high-quality results under tight deadlines.
• Additional expertise in power planning, routing strategies, and a deep understanding of IC fabrication processes.

• Telugu
• English

• Father's Name: K. VENKATESWARLU
• Date of Birth: 12/31/95
• Gender: Male
• Address: D No:5-1, Akkapalli Village, Racharla Mandal, Prakasam District, Andhra Pradesh , Pin - 523372

I hereby declare that the information given above is true to best of my knowledge.

Name- Venkata Rayudu Kuppala

Location- Bangalore