VENKATESH V CHAVADEKAR

Physical Design Engineer with relevant 5+ years of work experience,

team player with strong problem solving skills, contributed to team effectively on multiple complex projects, seeking a position to use my skills and in improving it.

• Floorplannning based on relevant Data flow defined in architectures.
• Addressed Setup timing convergence issues on CGC cells.
• Did Custom Clock Implementation for Clock latency reduction, which helped to reduce the number of levels in clock path and improved the clock tree dynamic power.
• Reduced more than 20% Buffers for hold fix In Post CTS Optimization by tweaking Clock ID for memories in mem2reg and reg2mem paths.
• Developed slack borrowing procedure for reg2reg paths has reduced unnecessary hold optimization.
• Developed the python script to reduce the time usage of user for launching sign off runs.
• Converged the critical design by cleaning more than 80% of the shorts In a hotspot by finding a precise solution.
• Developed Python scripts for Automation.
• Has Been part of the CAD Team for Initial Flow Flush of a modem subsystem.
• Developed a procedural tcl script based on trigonometric math function to reduce back to back hold buffers on less combo paths. was able to reduce 10% buffers from MEM2REG paths and REG2MEM paths.
• Reduced the leakage more than 50% in the design optimization, by applying the right timing related constraint.
• Worked On Dynamic IR drop reduction by using PG augmentation and load reduction procedures.
• Vector based and Vectorless based Dynamic IR Drop Reduction.
• FV CLP Debugging and analysis.