Summary
Overview
Work History
Education
Skills
Certification
Patents
Publications
Timeline
Generic

Venkateswaran Padmanabhan

Analog Mixed Signal Verification & Validation + Machine Learning Expert
Bengaluru,India

Summary

Venkat is Lead Professional with Overall 19+ Years of Industrial Experience cutting across Automotive , Industrial Sensors , Semiconductor & IOT sensors Domains. Venkat, a leader, influencer and prolific inventor in the AMS domain, is best known for early adoption of Machine Learning and A.I. principles to solve complex analog simulation problems including accurate PSPICE behavioral model for Customer Applications and accurate modeling of MOS impact ionization and self-heating characteristics. Venkat has collaborated with many BUs across TI to understand the pain points of analog designers and verification engineers in detail and has come up with numerous productivity tools to improve NPDE efficiency such as MLDV (Machine Learning for Design Verification), OPtiMem (OTP Interface Automated Digital Design & Verification flow) suite, Automotive dv suite (Automotive standards design verification bench) suite. Venkat is the champion of a vision to improve DV throughput by 10X and has set the stage in TI Power Switches Business, achieving 5X DV throughput on 30+ cores [2020-2024] addressing a net revenue >40 M$ through multiple innovation and automation initiatives. Venkat holds 8 Patents (2 granted ,5 filed ,1 disclosed), 15 publications which includes 12 internal TI conferences & 1 DAC ,1 IEEE ISQED’24, 1 National Instruments Test Summit. Venkat is a strong technical ambassador for TI through hands-on University collaborations at Tier 1 colleges in India sourcing bright talent through internships. Venkat is also a mentor in the verification community promoting knowledge sharing and talent development.

Overview

23
23
years of professional experience
6
6
years of post-secondary education
4
4
Certifications

Work History

Design Verification Manager

Texas Instruments India , Bangalore
8 2020 - Current

Responsibilities

  • Lead & manage a team of 15 mixed signal dv & digital design engineers
  • Collaborate with cross functional and project managers for project execution and delivering results silicon verification sign-off
  • Lead DV for Analog Power Switches TPS25984,TPS25985,TPS25990,LM74900,LM74912,TPS4811 ,TPS4810 family of devices,which involves system to design verification spec mapping , verification test bench development, system verilog test case development, design simulation & design functional & specification compliance verification
  • Drive automation initiatives across DV teams with the goal of DV throughput optimization

Key Achievements

  • Successful accomplishments in design verification throughput for 30+ Analog power devices released to market in 2.5 years
  • MLDV Suite(Rapid Adoption of Machine Learning @Design Verification): Manual waveform review is the biggest bottleneck in DV for every analog schematic iteration. Speed vs Accuracy vs Domain Skill plays a larger role in determining the quality and cycle time of reviews. Automation of the DV waveform review requires golden reference for every analog simulation timesteps & developing a golden device reference model is highly complex as it needs close resemblance to the device. Venkat is the primary inventor and architect of the ML toolkit which creates a DUT golden reference model using simulation logs as training set, Venkat invented a custom ML algorithm to bring formalism into analog space and achieve higher accuracy. Impact since 2020 this led to 100+ weeks cycle time reduction by automating the waveform review of 100K regressions and achieving faster & error free DV waveform review.
  • PMBUS UVM Automation (Automated PMBUS digital verification integrated with UVM flow) Verification of physical layer of Telemetry devices involves multiple technical challenges catering to complex and large number of checker development to establish correctness and coverage. Venkat invented the U-DMV (UVM integrated Digital Measurement & Verification) approach which is an integrated one stop solution for PMBUS-VIP integration into U-Made along with automated digital protocol verification and architected a configurable python driven flow through which the level of verification can be configured and can be integrated to simulation Impact : First telemetry product from TI power switch with 0 bugs detected in physical & datalink layer at post-silicon with successful on-time customer sample delivered to IBM, Tejas network, Juniper.

Talent Development

  • Mentored 25+ engineers in the areas of pre-silicon design verification through on the job and knowledge share sessions.
  • Tech Conference Chair: Collaborated with 20 Tech ladder title holders to solicit and review ~55 papers to choose presentations, posters, and demos for the conference.

Silicon Validation Architect

Texas Instruments
09.2017 - 08.2020

Responsibilities

  • Leading Post Silicon Validation Platforms Development.
  • Collaboration with Global Engineering & Cross Functional Teams .

Key Achievements

  • VASS (Validation Automation Software Suite): Validation of multiple devices is one of the biggest bottlenecks in post-silicon which requires the right engineering skillset & huge development effort in every product line across TI WW, this involves repeated ramping up of team members on domain skills and automation development effort. Venkat co-architected and developed VASS which is a world-class toolset that is used by every Analog Product line . The VASS identifies the common aspects of every analog product and automates the validation flow for every stage from synchronizing with input definition, validation sequence generation till spec results data upload. Impact with over 700+ devices worldwide the usage of the suite enabled 800+ man months savings across TI for the past from 2017-2020.

Talent Development

  • [2017-2020] Mentored 40+ validation engineers across analog product lines through knowledge share sessions on best practices for validation automation development techniques.
  • [2019] Conducted Workshop for TI WW 20+ engineers on TestStand Semiconductor Module which enables multisite programming for wafer-level and final package test applications .

<p>Project Leader ( Sensors & IOT)</p> <p></p>

Honeywell Technology Solutions Lab
04.2010 - 08.2017

Responsibilities

  • Leading Software Architecture Design and Development for Embedded Industrial , Automotive & IOT enabled sensors .
    Resource Planning ,Prioritization & Competency building.
  • Mentoring Six Sigma Green Belt project teams.

Key Achievements

  • Pressure Sensor Calibration Software Development Cycle Time reduced from 134 days to 52 days & cost savings of 100K USD per pressure sensor ATE bench through Six Sigma Back Belt Certification
  • Developed Pressure Sensor Calibration Coefficient prediction algorithm through Six Sigma DMAIC principles and Statistical tools and techniques like Design of Experiment , Annova & Linear Regression which significantly helped the sensors design team on wafer selection.
  • Role of Architect and scrum master for I2C based Multi master & three tier architecture board which enables very high speed calibration and coefficient programming for 100 + pressure sensors at a given instance
  • Honeywell - Intel freight tracking system is a multi layer IOT framework partnered with Intel Corporation which enables the health tracking of high cost goods.Venkat played the role of project lead & architect in identifying the bottlenecks to expedite the prototype.


<p>Consultant</p>

Siemens Information Systems India Pvt Ltd,Bangalore
08.2004 - 04.2010

Responsibilities

  • Software Requirement Management ,Design ,Development , Testing
  • Automotive Electronic Control Units Test Automation 
  • Automotive Infotainment Embedded Software Development 
  • Hardware in loop testing

Key Achievements

  • In Lab Road Condition Simulator

    • Siemens VDO infotainment dashboard had multiple challenges in terms Fuel level detection for the TATA Indica unit at South Asian regions.
    • I had played the role of designer and developer in developing a in lab road condition simulator using micro controller and load box in 3 weeks which had helped to decode the issue faster and solve the problem in a very short duration.

<p>Senior Engineer</p> <p></p>

Soliton Technologies Bangalore
01.2002 - 08.2004

Responsibilities

  • Software Requirement Management ,Design ,Development , Testing
  • Real Time systems development on Medical , Industrial & Automotive Domain System

Education

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BITS Pilani
01.2018 - 05.2020

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Coimbatore Institute Of Technology
11.1998 - 05.2002

Skills

Analog Mixed Signal Verification

Supervised & Unsupervised Machine Learning Algorithms

System Verilog & Cadence Ocean/Skill

Post-Silicon Mixed Signal Validation

LabVIEW Programming

Python & R Programming

Embedded & Microcontrollers

Sensors & IOT

Certification

Cadence System Verilog for Design and Verification

Patents

  • USPTO 82883911 "DESIGN VERIFICATION THROUGH MACHINE LEARNING " - A novel approach to perform pre silicon analog mixed signal waveform analysis . patent status "published" - https://ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20230409789
  • USPTO 82891700 - Machine learning techniques for analog circuit debugging- patent status "published" -https://ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20230409790
  • USPTO 82914174 "Method for Real Number System Verilog Model generation through Neural Network" - status - filed
  • USPTO 82898670 "Machine Learning Assisted Integrated Circuit Design Verification Methodology for Stepper Motor Drivers " status - filed
  • USPTO 82913820 " Machine Learning Driven PSPICE Device Modelling " - status - filed , industry's 1st machine learning generated PSPICE model uploaded to Ti.com -https://www.ti.com/product/TPS25961#design-tools-simulation

Publications

 

  • IEEE International Symposium on Quality Electronic Design "Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit Verification" [ Reference https://ieeexplore.ieee.org/document/10129327/authors#authors]
  • 60th DAC -2023 " Design Verification Waveform Analysis through Machine Learning Solution"
  • Texas Instruments internal conferences - authored & co-authored 16+ papers

Timeline

Cadence System Verilog for Design and Verification

10-2023

Certified Labview Architect

10-2020

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BITS Pilani
01.2018 - 05.2020

Silicon Validation Architect

Texas Instruments
09.2017 - 08.2020

Six Sigma Black Belt Expert

04-2017

Certified TestStand Developer

03-2017

<p>Project Leader ( Sensors & IOT)</p> <p></p>

Honeywell Technology Solutions Lab
04.2010 - 08.2017

<p>Consultant</p>

Siemens Information Systems India Pvt Ltd,Bangalore
08.2004 - 04.2010

<p>Senior Engineer</p> <p></p>

Soliton Technologies Bangalore
01.2002 - 08.2004

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Coimbatore Institute Of Technology
11.1998 - 05.2002

Design Verification Manager

Texas Instruments India , Bangalore
8 2020 - Current
Venkateswaran PadmanabhanAnalog Mixed Signal Verification & Validation + Machine Learning Expert