VENKATESWARA RAO REKAPALLI
BENGALURU
Summary
As a Physical Design Integration Engineer, I am part of a team working tirelessly to enable the silicon Armstrong era for the world. I work with complex designs, tools, and methodologies to deliver full chip with zero silicon issues for tape-ins. I have in-depth knowledge in the latest test chip designs with solid debugging skills for layout verification and layout design automation to reduce turnaround time.
Overview
3
3
years of professional experience
1
1
Certification
Work History
CAD Engineer
INTEL TECHNOLOGY PVT LTD
BENGALURU
08.2022 - Current
Worked on physical integration from the section level to the full chip level for the successful completion of tape-in.
Experience in layout automation, such as p-shifting, pwrvia, etc., using skill scripting.
Working for the regressive cell all clean (DRC, LVS, antenna, and density), integrating with the full chip, and taped in the Oasis.
Efficient in handling the full chip runs and analyzing the XOR runs for the latest test chips, 20A and 18A.
Worked on the development and validation of fill and PWRVIA enablement using the skill, Python, and designed various corner test cases for it.
Graduate Intern
INTEL TECHNOLOGY PVT LTD
BENGALURU
08.2021 - 07.2022
Working with pre-silicon validation of server processors, which deals with concurrency tests, validation of accelerator tests, tools development, etc.
Responsible for test development to validate firmware functionality for system-on-chip silicon and have exposure to the validation framework.
Working on Unified Patch Validation and understanding the logic of star codes.
Education
M.Tech - Microelectronics
MANIPAL INSTITUTE OF TECHNOLOGY
MANIPAL05-2022
B.Tech - Electronics And Communications Engineering
LAKIREDDY BALIREDDY COLLEGE OF ENGINEERING
MYLAVARAM04-2019
Skills
SKILL, Python, Verilog, TCL
Software tools: Synopsys ICV, Cadence Virtuoso
Accomplishments
Recognized multiple times in the team for the efficient work in handling full chip blocks for integration.
Gate qualified with 2200 rank in 2020 and 2019 ECE paper
Certification
Received NPTEL certificate in Network Analysis from IIT Madras and Control Systems from IIT Kharagpur with Elite performance.
Received NPTEL certificate in RTL to GDS flow from IIT Madras with Elite performance
Timeline
CAD Engineer
INTEL TECHNOLOGY PVT LTD
08.2022 - Current
Graduate Intern
INTEL TECHNOLOGY PVT LTD
08.2021 - 07.2022
M.Tech - Microelectronics
MANIPAL INSTITUTE OF TECHNOLOGY
B.Tech - Electronics And Communications Engineering
LAKIREDDY BALIREDDY COLLEGE OF ENGINEERING
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