Ranjith V N K Vetcha

Hardware Design and Validation Engineer

Wipro Technologies Ltd

Bangalore

06.2016 - Current

Currently working as a technical lead for the Power Design and Validation.
I have experience working on high-speed network routers, switches, and micro switches.
Worked on selection, characterization, and analog circuit designs for high-speed SerDes (>100G) interfaces, ASICs, FPGAs, PHYs, voltage regulators, level translators, clock generators (PLLs and DLLs), etc.
Schematic Capture - Allegro Design Entry HDL, Bill of Materials (BOM) creation, Assembly and Fabrication Process, PCB Layout Review.
Well-versed in PCB-level DC/DC power supply design (Switching Converters, LDO, Boost/Buck/Fly-Back regulators) and validation (Loop stability analysis, Dynamic load response, Efficiency testing, Overshoots/Undershoots, OCP, Duty cycle jitter tests, Voltage margining, Ripple/noise mitigation at various temperature corners).
Worked on front-end power supply (AC/DC converters) testing: SAG, line ramp, voltage disturbance ride-through, power disturbances, PSU load sharing, startup/holdup time, and FEP efficiency in variable environments.
Have a good understanding of the design of standard interfaces: I2C, SPI, PCIe, LVDS, LVPECL, USB, MDIO.
Worked on board-level power budgeting, power tree, power sequencing, voltage margining, and Power over Ethernet (PoE).
Good debugging skills and experience in product sustenance, dealing with field issues.
Collaborated with different cross-functional teams to ensure product quality and reliability.
Good experience in handling design layouts (Cadence), schematics (Cadence), BOM files, and net lists.
Experience in the hardware development life cycle involving functional requirements, circuit design, schematic entry, board bring-up, hardware troubleshooting, debugging the issues, and solving.
Tools used: Mixed Signal Oscilloscope, Frequency Response Analyzer, DC Electronic Load, Power Meter, IXIA Traffic Generator, JTAG Debugger, CMW, Chroma AC/DC Power Supplies, Edgar (POE Load), and Intel Platform Tools.
Have basic experience in EMI/EMC compliance testing of telecom products, with a relevant understanding of requirements, test planning, and execution of compliance tests such as radiated/conducted emissions, radiated/conducted immunity, ESD, harmonics, flickers, EFT, surge, V-dips, and interruptions.
Had solid experience in ATIS/TEER testing on Cisco switches.
Had basic knowledge of ADAS.
Low-power DC-DC converters modeling and analysis.
DC-DC converters testing and AC-DC power supply testing.
System-level testing and debugging.
Specification derivation and creation of a test plan.
Handling client interactions, technical discussions, and reviews.
Schematic capture and layout design tools: Cadence Allegro.
Analog Circuit Design.
Utility software: Linux terminal software, like Tera Term.
Programming languages: Verilog, C, Basics of Python, TTL Scripting.
Specialized tools: Cadence OrCAD Capture, Allegro Physical Viewer, LabVIEW, PSpice.
Developed validation protocols for process equipment and systems.
Performed risk assessments on new processes and equipment.
Provided clear and concise cost and time estimates for each phase of testing from test phase planning to final regression testing.
Authored and executed qualification protocols for clean utilities, HVAC, and manufacturing processes.
Maintained accurate records of all tests performed throughout the entire life cycle of a product or system.