Summary
Overview
Work History
Education
Certification
Achievements
References
Timeline
Generic

Vijay Mani

SoC Design Engineering Manager
Bengaluru

Summary

Highly motivated Delivery and Technical Lead with 14+ years of comprehensive experience in SoC design (front-end and back-end), micro-architecture, and application engineering. Proven track record of leading and driving successful subsystem integrations, collaborating effectively with SoC architects and IP micro-architects. Possesses a deep understanding of low-power design principles and expertise SoC Integration and other domain collaborations to ensure project success. Demonstrates exceptional proficiency in implementation techniques, including writing functional ECOs and developing timing constraints. Adept at managing teams, fostering a collaborative environment, and motivating team members to achieve peak performance. Seeks a challenging SoC Design and Implementation role to leverage extensive expertise and contribute to cutting-edge projects.

Overview

18
18
years of professional experience
1
1
Certification

Work History

SOC Design Engineer Manager

Intel technology Pvt Ltd.
5 2018 - Current
  • Experience in handing SubSystem.
  • Currently handling 7 configurations in the existing SoC which includes 3 Variants of Pcie, CXL and UCie based Subsytems
  • Managed SoC IP selection process for key building blocks within the SoC architecture, leading to significant cost savings without compromising system performance.
  • Delivered high-quality RTL code for complex blocks within aggressive project schedules, meeting or exceeding all performance targets.
  • Proactively identified potential bottlenecks in the design flow by conducting regular status updates and monitoring progress against established milestones.
  • Mentored junior engineers on best practices in SoC design engineering, fostering a culture of continuous improvement and technical excellence.
  • Supported product development lifecycle from concept to production, ensuring seamless integration of SoC components.

Technical Lead

Mirafra Software technologies
04.2015 - 05.2018
  • Maintained close communication with clients throughout project life cycles for accurate progress reporting and prompt issue resolution.
  • Constraint development- SPOC of the Sub-System
  • Design Synthesis and other implementation-related checks such as CLP, Formal Equivalence, and Constraint Validation
  • Owned power intent part of the design to ensure the correct intent is captured to by validating the intent using Low power checks.
  • My role majorly involves full front-end implementation

Senior Engineer

Larsen and Toubro Technology Services
06.2011 - 04.2015
  • HW Trace Implementation: Built into SoC to analyze, correct, and display internal data. Data signals for trace capture are multiplexed into an on-chip trace buffer. Data can be analyzed by on-chip CPU/DSP or other hardware and accessed via JTAG Debug, USB, or Ethernet channels.
  • Design Work: Created memory, CPS trace blocks, DDRTM, and GTM trace blocks. Developed constraints for block design synthesis.
  • Integration and Verification: Integrated and functionally verified Phy IP, including standalone loopback functionality of the SerDes. Designed interrupt logic for PHY.
  • Phy Integration: Integrated SerDes IP with the Ethernet complex block, gaining knowledge of the Ethernet PCS layer.
  • Design and Synthesis: Performed synthesis using Design Compiler and Design Compiler Topo Graphical. Conducted logic equivalence checks with Cadence Conformal and collaborated with the Physical Design team to meet timing and area requirements.
  • Constraint and ECO Management: Implemented Functional ECOs using TCL, including critical manual efforts. Managed constraint validation for pre- and post-layout stages and conducted STA for constraint validation. Optimized designs through logic synthesis experiments.
  • FEV: Executed formal verification of pre- and post-layout netlists against RTL to ensure design integrity.
  • SerDes IP Challenge: Worked without HAS/MAS or documentation, learning the IP basics to make it functional using default simulation settings.
  • Established and maintained productive working relationships with stakeholders.

Trainee Engineer

RF Silicon Pvt. Limited
11.2010 - 05.2011
  • Collaborated with senior engineers on complex projects.
  • Enhanced team productivity with regular progress reviews, feedback sessions, and implementing necessary adjustments.
  • Supported senior engineers in research and development activities, leading to innovative solutions for complex engineering challenges.

RF Broadcast Engineer

11.2006 - 07.2007
  • Kept signal strong, clear, and reliable with continuous monitoring and optimization of broadcast equipment.
  • Adjusted controls on station console to regulate transmission fidelity, contrast, and brightness.
  • Worked with sound engineers to strengthen audio and video quality during broadcasts.
  • Supported remote broadcasts successfully by setting up satellite uplinks, or other mobile transmission equipment as needed.
  • Trained junior engineers on broadcast procedures, enhancing overall team performance and knowledge base.

Education

Master of Science - Microelectronics And System Design

Liverpool John Moore's University
Liverpool UK
04.2001 -

Bachelor of Science - Electronics And Communications Engineering

Apeejay College of Engineering
Haryana
04.2001 -

Diploma in Electronics And Communications

Fr. Agnel Polytechnic
New Delhi, India
05.2003

Certification

Completed Power electronics course from IIT-Mumbai: Certification Received.

Achievements

  • Proposed Main-band Dynamic Power gating technique
  • Actively participated in Post Silicon debug sessions related to PCie and CXL Sub-System
  • DTTC Paper Published 2024: Impact of PSF pipe-stages on IO performance
  • DTTC Paper Published 2023: PCIe CXL Sub-System construction: Challenges and Learnings

References

Available on request

Timeline

Technical Lead

Mirafra Software technologies
04.2015 - 05.2018

Senior Engineer

Larsen and Toubro Technology Services
06.2011 - 04.2015

Trainee Engineer

RF Silicon Pvt. Limited
11.2010 - 05.2011

RF Broadcast Engineer

11.2006 - 07.2007

Master of Science - Microelectronics And System Design

Liverpool John Moore's University
04.2001 -

Bachelor of Science - Electronics And Communications Engineering

Apeejay College of Engineering
04.2001 -

SOC Design Engineer Manager

Intel technology Pvt Ltd.
5 2018 - Current

Diploma in Electronics And Communications

Fr. Agnel Polytechnic

Similar Profiles

CREATE PROFILE
Vijay ManiSoC Design Engineering Manager