Vijaya Kumar Vinukonda

• Successful completion of Samsung platforms (11LPP, 14LPP, 14LPU, etc) development including various logic, Memory and IO products

• Leading development of various Interface/IO products, like GPIO and high frequency Speciality IO (like DDR, LVDS, LPDDR, subLVDS, USB, I2C, etc)

• Architect for various IO products and build culture of innovations within the team.

• Silicon experience with all major foundries (like TSMC, Samsung, GF and other Foundries as well) involving in various technology nodes (from 180nm to latest 3nm)

• Successfully build products from various leading customer requirements to a specific application and end-product (like Client/Mobile, Automotive, Infrastructure and IOT/Low Power)

• Deeply involved in building ESD protection architecture and packaging requirements and constraints for Interface/IO products.

• Leading and managing IO, Analog and Mixed Signal (AMS) product team (globally) across different design centers and cross-functional teams to deliver high-quality products.

• Leading product specific steering and working groups for planning and building product architectures, workflows, policies, methodologies, development flows and EDA requirements.

• Pro-active contribution in pre-sales, marketing, commercial and customer interactions to successfully convert requirements to deliver silicon qualified products.

• Actively involved in driving Testchip and silicon test and PFA (Physical FA) requirements and methodologies for Logic, Memory, IO, ESD and AMS products

• Maintained up-to-date knowledge of industry standards, policies and regulations and ensured team compliance.

• Collaborated with stakeholders, including customers, vendors, and internal teams, to ensure successful product delivery and customer satisfaction.

• Design experience of Dual Port SRAM products, involving Architecture, bitcell analysis, IO Buffer design, Row/column redundancy and Full Chip Functional & timing Simulations

• Involved in silicon qualification and debug of SRAM products.

• Build Verilog models for SRAM products and completed with full verification.

• Actively involved and completed full chip simulations of Zero delay buffer including PLL and LVCMOS Input Receiver and Output Buffer.