VIJAYA LAKSHMI A

Project 1: MI450 (AMD)

Duration : Feb 2024 - Nov 2025

• Technology : 3nm
• Tools: Synopsys Fusion Compiler, PrimeTime, Cadence Innovus
• Design Size: ~1 M Instances | Target Frequency: 1.86GHz

Responsible :

- Worked on both single-power and multi-power domain tiles following advanced low-power methodologies.

- Performed complete physical design flow from floorplanning to signoff for multiple blocks.

- Executed congestion-aware floorplanning, macro placement optimization, and routing-driven timing closure.

- Performed manual ECOs and electrical fixes including data/clock transition violations, long net optimization.

- Collaborated closely with timing and power teams to meet PPA goals.

TRAINING PROJECTS

Project 1: DTMF

• Technology : 45nm
• Design Size: ~29.7K Instances | Hard Macros: 16 | Frequency: 125 MHz
• Implemented physical design techniques such as cell padding, bounding, and path grouping.
• Successfully closed timing on a congestion-critical block with tight area constraints.

Project 2 : PCI-TOP

• Technology : 28nm
• Tools: Genus, Cadence Innovus
• Design Size: ~27K Instances | Target Frequency: 1 GHz

Responsible :

- Handled a congestion-critical square block with aggressive timing requirements.

- Achieved timing closure through multiple optimized floorplan and placement iterations.

- Strong understanding of advanced-node physical design challenges

- Hands-on experience in timing ECO closure and electrical rule fixing

- Ability to work independently on block ownership

- Good collaboration with cross-functional teams

Project 3 :ASIC entity

• Technology = 7nm
• Instances 250K
• Hard Macros: 32
• Frequency: 125 MHz

Responsible

- Invovled in full physical design cycle from floorplanning to GDSII delivery.- Performed macro placement planning, power grid implementation, and CTS optimization. - Resolved congestion issues using module placement constraints and path grouping techniques. - Closed setup and hold timing across all corners.