Vikal Chandra

• Working on a image sensor project and developing some mathematical algorithm based RTL Design using Verilog.
• With extensive expertise in RTL design, Verilog, SV, Debugging, Lint, CDC, STA, Verification, and Simulations.
• Experience with Xilinx FPGA Board and complete FPGA flow RTL Design, Simulations, Synthesis, Mapping, Place and Route, Implementation, Bit stream generation, debugging.

Client: Keysight Technologies Pvt Ltd

• Worked on I2c, SPI, UART, FlexRay, PCIe and CXPI Protocols for automotive projects.
• Written various modules in Verilog for protocol development
• With extensive expertise in RTL design, Verilog, SV, Debugging, Lint, CDC, STA, Verification, and Simulations.
• Experience with Xilinx FPGA Board and complete FPGA flow RTL Design, Simulations, Synthesis, Mapping, Place and Route, Implementation, Bit stream generation, debugging.

• During this project, I collaborated with the team to focus on the RTL design of different AMBA protocols such as APB, AHB, and AXI. To ensure the functionality of the designs, I utilized the cadence Incisive tool and a test bench for verification. Additionally, I employed linting tools to identify and address any design violations.
• I worked with Verilog, System Verilog, UVM, Lint, CDC, Debugging, and Simulations.

• Serial Adder design- Using Verilog, SV
• APB Memory design-Design of RTL for APB protocol-based memory (1kx32) and development of test bench for verification
• Hand-on experience in ASIC/ FPGA/ SOC Design and Verification
• Experience with performance analysis, optimizations, and test bench