Vimlesh Kumar
Physical Design Engineer
BENGALURU
Summary
Working as Senior Lead Design Engineer at NXP Semiconductor with 10 years of experience in Physical Design, Physical Verification and IR analysis. Worked on over 11 projects till tape out.
Overview
10
10
years of professional experience
4
4
years of post-secondary education
1
1
Certification
Work History
Senior Lead Design Engineer
NXP Semiconductor
BENGALURU
2021.06 - Current
- Full Chip ownership for IR signoff, Responsible for IR signoff runs and methodology improvements
- Worked on EM methodology, Ramp up analysis, Vmin analysis and DFT IR runs
- Responsible for Mix level PDN sign-off quality and Methodology improvements
- Responsible for PnR for always-on block with 1 million instances from Floorplan till GDS delivery.
Physical Design Engineer
Intel Technology India
BENGALURU
2020.03 - 2021.06
- Utilized state-of-the-art EDA tools to perform detailed place-and-route operations for multi-million gate designs successfully.
- Block level ownership from Floorplan till GDS delivery
- Responsible for delivery of Floorplan, CTS and Routed data with Signoff quality
Worked on LEC, CLP, PDN, DRC, LVS and Signoff STA. - Worked on Camera Block for automotive use with over 2 million instances based on 16nm technology node
- Worked on three Graphics chips based on 14 nm and 10nm technology node with 12 metal layers
- Developed custom scripts for improved design flow efficiency, boosting productivity within team
Senior Physical Design Engineer
Si2Chip Technologies Pvt. Ltd.
BENGALURU
2017.04 - 2020.03
- Ownership of complex low power blocks in Qualcomm and Samsung with multimillion gates
- Responsible for Floorplan, Placement, CTS, Routing and GDS convergence of block with ~4000 high frequency Feedthrough nets including clock nets
- Improvements achieved in terms of congestion and routing of design by planning at floorplan and signoff stage
- Sign-off STA for creating ECOs for final timing fixes
- Worked on skew fixes of camera blocks and DDR test chip.
- Solved issues with SDC constraints causing negative MPW violations
- Worked on 10nm and 7nm technology nodes.
- Collaborated with cross-functional teams to ensure smooth project execution and timely delivery of designs
- Developed custom scripts for improved design flow efficiency, boosting productivity within team
Physical Design Engineer
Intel Technology India Pvt. Ltd.
BENGALURU
2015.09 - 2017.04
- Block level ownership from Floorplan till GDS delivery
- Responsible for delivery of Floorplan, CTS and Routed data with Signoff quality
- Worked on LEC, CLP, PDN, DRC, LVS and Signoff STA.
- Worked on Camera Block for automotive use with over 2 million instances based on 16nm technology node
- Worked on three Graphics chips based on 14 nm and 10nm technology node with 12 metal layers
- Developed custom scripts for improved design flow efficiency, boosting productivity within team
Field Application Engineer
Trident Tech Labs Pvt. Ltd.
Hyderabad
2014.12 - 2015.08
- Owned block-level physical verification closure
- Working closely with design teams in defense labs (DRDO, DAE), helping them to achieve DO-254 standards in FPGA design using EDA tools from Mentor Graphics
- Imparting training on EDA tools and related technology like Functional Verification, RTL Synthesis, Layout design, Physical verification, Requirement Tracing.
- Maintained effective customer relationships and identified future business opportunities to support and strengthen corporation mission
- Developed comprehensive training materials for clients, ensuring proper utilization of products and services
- Established strong relationships with clients by offering personalized solutions to meet their unique requirements
Education
B.Tech - Electronics and Communication Engineering
CCS University
Meerut , Uttar Pradesh 2009.08 - 2013.06
Skills
Power Grid Design
Clock Tree Synthesis
Static Timing Analysis
Design Rule Checking
Certification
Introduction to Device and System packaging
Timeline
Senior Lead Design Engineer
NXP Semiconductor
2021.06 - Current
Physical Design Engineer
Intel Technology India
2020.03 - 2021.06
Senior Physical Design Engineer
Si2Chip Technologies Pvt. Ltd.
2017.04 - 2020.03
Physical Design Engineer
Intel Technology India Pvt. Ltd.
2015.09 - 2017.04
Field Application Engineer
Trident Tech Labs Pvt. Ltd.
2014.12 - 2015.08
B.Tech - Electronics and Communication Engineering
CCS University
2009.08 - 2013.06
Introduction to Device and System packaging
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