Vinayak Dabholkar

Worked in a small team and taped-out 3 chips of HBM2/HBM2E. Worked on customer IP releases for HBM2/2E customers. Owned RTL design , lint and CDC of entire IP.

RTL design involved Hard-PHY changes as per PD requirements. Soft-PHY changes as dictated by Hard-PHY. Added logic to Soft-PHY to auto train DDR interface with inputs from Architect and later owned the complete design for bug fixes and new enhancements.

Supported customer chip bring ups for HBM2

Owning again the front end for Hard PHY and Soft-PHY for HBM3 IP. Taped-out 2 test-chips and supported validation for chips in house.

Owned a key component to enable Auto interface training in LPDDR5 IP and provided support to new members to ramp up.