Summary
Overview
Work History
Education
Skills
Languages
Timeline
Generic

Vinothkumar Sathasivam

Summary

With 8.4 years of experience as an Lead Design Engineer , with a proven track record at LeadSoc Technologies India Pvt Ltd, I excel in SOC and IP design optimization, significantly reducing production costs. Skilled in EDA tools and adept in team leadership, my expertise in LINT, CDC, and RDC concepts has consistently enhanced design performance and efficiency.

Overview

9
9
years of professional experience

Work History

Lead Design Engineer

LeadSoc Technologies India Pvt Ltd
09.2020 - Current

Client : NXP Semiconductors, Bengaluru .

  • Responsible to integrating blocks in the SOC core design using RIT tool.
  • Responsible to complete LINT, CDC, RDC & Synth elaboration checks on SOC/SS/IP Design. Using EDA tools.
  • Experienced with netlist CDC analysis using Questa CDC signoff tool.
  • Delivered comprehensive design documentation to customer & backend team, etc..

Senior RTL Design Engineer

Pozibility Technologies Pvt Ltd
02.2020 - 06.2020
  • Worked on in-house projects to enable the LINT & CDC check on IP design using Spyglass LINT/CDC tool.

Design Engineer

Excelmax Technologies Pvt Ltd
10.2019 - 02.2020
  • Worked on in-house projects to complete the LINT and CDC checks.
  • Optimized existing designs, reducing production costs and enhancing overall performance.

Design Engineer

SeviTech Systems Pvt Ltd
04.2018 - 09.2019

Client: Western Digital, Bengaluru

  • Worked on multiple SOC designs with 16 nm technology, to complete the LINT & CDC check clean.

Design Engineer

SmartDV Technologies India Pvt Ltd
10.2015 - 09.2017
  • Worked on multiple IP level designs to clean LINT & CDC checks. Writing the CDC constraints for different projects.
  • Optimized existing designs, reducing production costs and enhancing overall performance.
  • Managed multiple projects simultaneously.

Education

BE (Part-Time) - Electronics And Communication Engineering

Vinayaka Missions Kirupananda Variyar Engineering
Salem, Tamil Nadu, India
05-2022

Diploma - Electronics And Communications Engineering

Thiagarajar Polytechnic College
Salem, Tamil Nadu, India
05-2015

H.S.C - 12th Passed With 52%

Bharathi Vidyalaya Senior Secondary School
Salem, Tamil Nadu, India
05-2013

S.S.L.C - 10th Passed With 85%

Ammapet Municipal Boys Higher Secondary School
Salem, Tamil Nadu, India
04-2011

Skills

  • Expertise SoC integration
  • Expertise LINT, CDC & RDC concept
  • Good experience in EDA tools
  • Write script for automation
  • Good experienced in debugging design functional failure
  • Continuous improvement mindset
  • Technical documentation mastery
  • Supporting DE/Methodology team to improve the EDA checks
  • Team leadership
  • Reverse engineering techniques
  • Problem-solving
  • Quality assurance
  • Design development
  • Process development

Languages

Tamil
Bilingual or Proficient (C2)
English
Bilingual or Proficient (C2)

Timeline

Lead Design Engineer

LeadSoc Technologies India Pvt Ltd
09.2020 - Current

Senior RTL Design Engineer

Pozibility Technologies Pvt Ltd
02.2020 - 06.2020

Design Engineer

Excelmax Technologies Pvt Ltd
10.2019 - 02.2020

Design Engineer

SeviTech Systems Pvt Ltd
04.2018 - 09.2019

Design Engineer

SmartDV Technologies India Pvt Ltd
10.2015 - 09.2017

BE (Part-Time) - Electronics And Communication Engineering

Vinayaka Missions Kirupananda Variyar Engineering

Diploma - Electronics And Communications Engineering

Thiagarajar Polytechnic College

H.S.C - 12th Passed With 52%

Bharathi Vidyalaya Senior Secondary School

S.S.L.C - 10th Passed With 85%

Ammapet Municipal Boys Higher Secondary School
Vinothkumar Sathasivam