Summary
Overview
Work History
Education
Skills
Certification
Timeline
Generic

Vishal Kumar Bind

Hyderabad

Summary

Reliable professional committed high-quality work. Skilled in helping modernize workplaces and maintaining high levels of work ethics. Resourceful and personable with excellent multitasking abilities.

Overview

1
1
year of professional experience
1
1
Certification

Work History

Intern(Front End Developer)

Timing Technology India Pvt Ltd
Hyderabad
06.2023 - Current
  • Designed and implemented interactive user interfaces for websites.
  • Resolved cross-browser compatibility issues for consistent look across different platforms.
  • Debugged existing code to identify and fix bugs or performance issues.
  • Gained experience in HTML and CSS for building pages and styling the pages.
  • Developed and maintained user-friendly webpages using HTML, CSS, JavaScript.
  • Learned how to create responsive web pages and Mobile friendly web design.
  • Collaborated with Senior Developer and worked with different team members.

Education

B. Tech - Electronics And Communications Engineering

CMR INSTITUTE OF TECHNOLOGY
Medchal, TG
08-2023

MPC -

Narayana Junior College
Madhapur
03-2018

SSC -

Newton High School
Madhapur, TG
03-2016

Skills

  • Python basic
  • Front End Web Development
  • Back End Web Development
  • SQL
  • Problem Solving
  • Basic Knowledge on Command Line
  • Analytical skills
  • Fast Learner
  • Hard Worker
  • Good team work
  • Collaboration and Communication

Certification

Verilog HDL and VLSI hardware Design

  • Familiar with basic logic gates like AND, OR, NOT, etc. and their truth tables. Understand how Boolean algebra applies to digital circuits.
  • Learned difference between combinational and sequential logic circuits. Understand flip-flops, latches, and their applications.
  • Learned Verilog syntax, module declaration, data types like reg, wire, integer, etc., and basic constructs (always blocks, initial blocks).
  • Learned Behavioral Modeling, Dataflow Modeling, Structural Modeling
  • Learned Basic CMOS Circuit

Digital Marketing

Certificate of Appreciation in event ILLUMINATE 2022

Timeline

Intern(Front End Developer)

Timing Technology India Pvt Ltd
06.2023 - Current

B. Tech - Electronics And Communications Engineering

CMR INSTITUTE OF TECHNOLOGY

MPC -

Narayana Junior College

SSC -

Newton High School

Verilog HDL and VLSI hardware Design

  • Familiar with basic logic gates like AND, OR, NOT, etc. and their truth tables. Understand how Boolean algebra applies to digital circuits.
  • Learned difference between combinational and sequential logic circuits. Understand flip-flops, latches, and their applications.
  • Learned Verilog syntax, module declaration, data types like reg, wire, integer, etc., and basic constructs (always blocks, initial blocks).
  • Learned Behavioral Modeling, Dataflow Modeling, Structural Modeling
  • Learned Basic CMOS Circuit

Digital Marketing

Certificate of Appreciation in event ILLUMINATE 2022

Vishal Kumar Bind