Vishnu Vardhan Reddy Erigela
Choutapally, Suryapet
Summary
- Front-end design verification engineer with 7+ years of experience in the semiconductor industry. Possesses a strong technical background, and problem-solving skills, to handle the tasks efficiently. Proven ability in delivering products with best quality by creating comprehensive test plans and implementing them using SystemVerilog, OVM, and UVM.
Overview
8
8
years of professional experience
Work History
IP Design Verification Engineer
Intel Technology India Pvt. Ltd.
Hyderabad
11.2021 - Current
- Project:
- Secure Platform Boot Controller (SPBC) IP for various generations of Intel client and server SoCs.
- Responsibilities:
- Executed front-end design and verification from specification to IP sign-off.
- Developed comprehensive verification plans for new features, ensuring thorough testing and validation.
- Maintained legacy test suites to ensure continued performance and reliability.
- Enhanced testbench functionality through testcase development and scoreboard implementation.
- Root-caused regression failures, collaborating with RTL designers to implement solutions.
- Validated new IP blocks via formal verification processes to ensure compliance with specifications.
- Analyzed code coverage, addressing gaps to improve overall verification quality.
- Reproduced silicon bug sightings in the IP environment.
- Mentored junior engineers on best practices in design verification, fostering skill development.
Engineer
Tech Mahindra Cerium Systems
Bengaluru
02.2018 - 11.2021
- Projects:
- North Peak (NPK), 04/2021 - 10/2021.
- Secured Platform Boot Controller (SPBC), 11/2019 - 03/2021.
- Power Management Validation Collaterals (PM VC), 02/2018 - 10/2019.
- Responsibilities:
- Developed BFMs from scratch.
- Created trackers to monitor all features effectively.
- Implemented scoreboard and SVA-based checks to ensure compliance with specifications.
- Coded test cases and ensured functional coverage to validate feature integrity.
- Verified new IP features using formal verification techniques like Formal Property Verification (FPV) and Sequential Equivalence Checking (SEC).
- Conducted regression triage and debugged failures to maintain software stability.
- Assisted customers with VIP integration for seamless implementation.
Education
Advanced VLSI Design and Verification course - Bengaluru
Maven Silicon Softech Pvt. Ltd.
Bengaluru02.2018
Bachelor of Technology - Electronics And Communication Engineering
Nalla Malla Reddy Engineering College
Hyderabad, Telangana06-2017
Skills
- Verification planning and documentation
- Verilog and SystemVerilog
- OVM and UVM methodologies
- Functional and formal verification
- Assertion-based verification
- Coverage-driven verification
- Constraint random testing
- TestBench development
- Coverage analysis
- Regression testing and debugging
- Protocols: QSPI, eSPI, APB, AHB
- Verification tools: Synopsys VCS, Cadence JasperGold, Synopsys Verdi
- RTL design tools: Spyglass Lint, Spyglass CDC, RDC
- Scripting: Perl
Languages
Telugu
First Language
English
Proficient (C2)
C2
Timeline
IP Design Verification Engineer
Intel Technology India Pvt. Ltd.
11.2021 - Current
Engineer
Tech Mahindra Cerium Systems
02.2018 - 11.2021
Advanced VLSI Design and Verification course - Bengaluru
Maven Silicon Softech Pvt. Ltd.
Bachelor of Technology - Electronics And Communication Engineering
Nalla Malla Reddy Engineering College
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