Vidyut Patel
Pune
Summary
Senior Principal Design Engineer skilled in synthesis and static timing analysis. Specializes in physical design methodologies and formal verification, delivering optimized designs for high-performance AI accelerator IPs. Achieved significant improvements in timing closure and area optimization across multiple technology nodes.
Overview
15
15
years of professional experience
Work History
Senior Principal Design Engineer
Cadence
Pune
11.2015 - Current
- Executed physical implementation of multiple Cadence IPs across diverse technology nodes, ensuring high-quality design delivery.
- Contribute to next-generation DSP architecture development by collaborating with RTL teams to resolve complex physical design challenges.
- Optimized physical design of AI accelerator IPs, overcoming routing bottlenecks and improving scalability across platforms.
- Led physical optimization of Vision and Audio IPs, driving performance characterization and efficiency across technology nodes.
- Actively supported FUSA product development, recommending architectural enhancements to strengthen physical implementation.
- Developed and executed synthesis flow methodologies for Cadence IPs, streamlining design processes and reducing turnaround time.
- Established static timing analysis methodologies to enhance IP performance and reliability.
- Designed MBIST/LBIST flows to improve testing coverage and validation efficiency for Cadence IPs.
- Lead a team of 4 junior engineers, overseeing project execution and ensuring alignment with organizational objectives.
- Mentor and guide junior engineers on best practices in product development and project management, fostering team growth.
- Deliver technical presentations to stakeholders, effectively communicating project milestones, risks, and objectives.
ASIC Design Engineer
Smartplay Technologies (Qualcomm India Pvt Ltd.)
10.2013 - 11.2015
- Executed synthesis, formal verification, timing analysis, and timing closure for ASIC digital designs.
- Targeted 28nm TSMC technology for project with 550k gate count.
- Achieved timing closure at 550 MHz, overcoming area optimization challenges.
- Conducted static timing analysis to ensure design integrity and performance.
ASIC Design Engineer
Appsconnect Pvt. Ltd (SiconTech)
12.2012 - 09.2013
- Conducted static timing analysis and achieved timing closure for ASIC digital designs.
- Managed timing closure across various modes and corners independently.
- Addressed crosstalk effects impacting noise and timing integrity.
- Executed post-layout static timing analysis for projects targeting 90nm and 45nm TSMC technologies.
- Targeted clock frequencies of 800MHz and 400MHz for respective projects.
- Facilitated functional scan capture, scan shift, and MBIST modes during design implementation.
- Overcame challenges related to clock balancing for cross-domain paths and scan capture hold violations.
Senior Engineer
MindTree Pvt. Ltd
06.2011 - 11.2012
- Executed RTL analysis, synthesis, and static timing analysis for ASIC digital designs.
- Oversaw RTL modifications through to GDS II delivery within TI’s 180nm technology.
- Developed constraints ensuring design met timing requirements during synthesis setup.
- Utilized various techniques to optimize design timing throughout synthesis process.
- Conducted formal verification and debugging of pre-layout netlist against RTL.
- Created methodologies for CSOC/IPPOOL project, streamlining design flow from RTL to GDS II delivery.
Education
M.Tech - Information & Communication Technology (VLSI)
DhirubhaiAmbani Institute of Information & Communication Technology
Gandhinagar06-2011
Bachelor of Engineering - Electronics & Communication
Dharmsinh Desai University
Nadiad05-2009
Higher Secondary School Education -
Gujarat Education Board
03-2005
Secondary School Education -
Gujarat Education Board
03-2003
Skills
- Synthesis techniques
- Static timing analysis
- Physical design methodologies
- Formal verification processes
- Genus and Design Compiler
- Tempus and PrimeTime
- Innovus design platform
- Conformal and Formality
- Verilog and SystemVerilog
- AI Tools: GitHub Copilot in VSCode
- Tcl scripting
- Windows operating systems
- Linux environment
- C and C programming
- LTSpice simulation
- Xilinx ISE development
- ASIC digital design expertise
Mtech Thesis
Asynchronous Analog to Digital Converter, 01/2009 - 04/2009, Proposed architecture to reduce power consumption compared with existing conventional architectures.
Personal Information
- Date of Birth: 12/31/87
- Marital Status: Married
Training
e-Infochips Pvt. Ltd, 01/2009 - 04/2009, ASIC Verification Trainee, Verification of DSP Block in SYSTEM VERILOG Using MATLAB
Participation And Achievements
- Co-presented paper on MBIST Methodology for Tensilica IPs in CDNLive India,2019
- GATE-2010, 714, 554, Electronics & Communication
- GATE-2009, 542, 1085, Electronics & Communication
- CEP Course on Electromagnetic Waves And Transmission Lines, IIT Bombay Golden Jubilee Extension Centre, Gandhinagar, 02/2008
- POWER-2007 (Trekking Camp), Dalhousie – Amritsar – Jalandhar, 05/2007
- TECHNOFORA – 2007 (NATIONAL EVENT), Nirma University, Semi-finalist in Circuit Designing Competition
- RESONANCE – 2007 (NATIONAL EVENT), Dharmsinh Desai University, FM-Jammer
Summary
13, IC Design technology, Synthesis and Static Timing Analysis, Partition based top-down/bottom-up and flat Physical Design implementation, DFT flows such as LBIST/MBIST, VLSI background in ASIC Design and methodology development, Shell scripting and PERL scripting, Verification environment and System Verilog knowledge
Languages
- English
- Hindi
- Gujarati
Languages
English
Advanced (C1)
C1
Hindi
Advanced (C1)
C1
Gujarati
Proficient (C2)
C2
Timeline
Senior Principal Design Engineer
Cadence
11.2015 - Current
ASIC Design Engineer
Smartplay Technologies (Qualcomm India Pvt Ltd.)
10.2013 - 11.2015
ASIC Design Engineer
Appsconnect Pvt. Ltd (SiconTech)
12.2012 - 09.2013
Senior Engineer
MindTree Pvt. Ltd
06.2011 - 11.2012
M.Tech - Information & Communication Technology (VLSI)
DhirubhaiAmbani Institute of Information & Communication Technology
Bachelor of Engineering - Electronics & Communication
Dharmsinh Desai University
Higher Secondary School Education -
Gujarat Education Board
Secondary School Education -
Gujarat Education Board