Yadunandan Puttaswamy

Primary responsibility is to develop low level driver APIs for state of the art high end Infineon Aurix 3rd Gen Microcontrollers. Complete ownership and Technical Lead for Communication Cluster.

Includes:

Requirements, Register Header File Generation, Pinmaps, Derivative Configuration files, Architecture, C Code Implementation, Unit and System Functional Testing, Reviews, Demos, Board Schematics Review and Silicon Bringup.

Platforms: Virtual Prototype, Simulator, Emulator, Silicon.

Support stakeholders with IP understanding and API usage to develop test cases across platforms.

Provide Technical consultations for productive MCAL driver team.

Peripherals:

Developed form Scratch:

Gigabit Ethernet (Synopsis XGMAC 10M-5G), Lite Ethernet (Synopsis EQoS 10M-100M), Multiple Ethernet Multiport Bridges, Can and Ethernet Accelerators (CRE & DRE), CanXl.

Audio - Requirements phase done.

Reworked HSPHY(supporting XSPI, GETH, PCIE) for multi-module support and ASCLIN-(Uart, Lin, Spi)

Bug fixes, maintenance and updates:

QSpi, SENT, MCan.

Maintenance:

I2C, MSC, PSI5, PSI5s.

New Recent Addon: XSPI

Stacks: Lwip (Integration of Lwip to low level drivers)
Ethernet PHYs: RTL8201, RTL8211, RTL8221, DP83825
Ethernet modes: MII, RMII, RGMII, SGMII, 10Base-T1S

Automation and Scripting as required for various deliverables/test needs.

Provide training on IP, driver usage and applications.

TL Role: Interface for Project Management, Quality, Technical Stakeholders and Customers.

Process Review/Update/Compliance.

Continuous Improvements in the day to day working through refinement and automation.

Review User Manual, 3rd party IP Docs, Code, Tests, Demos, Register Headers, Register Grouping, Pinmaps, Derivative Configuration files, Test Reports, Release Plan, Release Notes, Bug analysis and workarounds.

Plan Demos and review Board Schematics.

Sprint Planning and assignment of tasks to team and work tracking for periodic releases.