Yogesh Sehrawat
WLAN PHY Designer
Bangalore
Summary
Result-driven ASIC Design Engineer having 7 years of experience in micro architecture development and RTL design with solid background in WLAN PHY. Strong engineering professional having exposure to complete ASIC cycle i.e., micro-architecture, RTL coding, Lint, CDC, Synthesis, STA and coverage analysis and experience of working on complex designs consisting of a million gates and up to 200k flops.
Overview
7
7
years of professional experience
6
6
years of post-secondary education
Work History
Senior Design Engineer
Synaptics Incorporated
03.2023 - Current
- Working on architecture/design of Demodulation controller and SIG field decoder for 802.11be Wi-F standard
- Leading team of two junior engineers, proving mentorship and guidance in designing Beamformee and De-scrambler
- Architecture/Design of WLAN PHY Rx sub-blocks including LDPC decoder and channel smoothing
- Extensive knowledge of 802.11 Wi-Fi standards including 11a/11n/11ac/11ax/11be
- Prepared and presented 802.11 be Wi-Fi standard to cross functional teams around globe
- Received exceptional contributor (PHY Team) award (Q4-2023) from SVP
Senior Lead Engineer
Qualcomm
09.2019 - 02.2023
- Architecture/Design of PHY Tx (frequency domain) sub blocks for 802.11be STA and AP.
- PHY Tx (Frequency domain) POC for low tier STA and AP chips.
- Designed programmable preamble generator and RU tone mapper.
- Re-Architected Tx control path and enhanced data path processing time by 1 micro sec.
- Re-Architected Tx data path for 320Mhz serial processing which resulted in area saving of ~50k.
- Coded RTL for design, provided end to end DV support, closed timing and coverage.
- Implemented low power design techniques for power optimization.
ASIC Design Engineer 2
Juniper Networks
07.2017 - 09.2019
- Performed block level design for switch fabric.
- Designed traffic scheduler that performs output port lookup for incoming traffic on basis of destination address. DWRR scheduling is implemented for load balancing across multiple output ports for traffic coming on input port.
- Designed output traffic generator that continuously serves incoming data requests (TFM multiplexed) for different links based on Ser-Des data rate. Credit return interface is also designed to fetch data from shared memory.
- Implemented high performance pipelines with necessary bypass logic for above designs.
- Developed micro-architecture from functional specifications to meet throughput with area and power optimization.
- Defined and implemented block interfaces and register sets.
- Coded RTL for micro-architecture implementation and worked with design verification team to develop test cases, debug and perform block level bring-up.
- Designed synthesizable traffic generator for FPGA prototyping of fabric chips.
- Implemented feature in shared memory manager to prevent re-circulation of memory pointers on parity error.
- Worked with team to perform full chip RTL integration.
Education
M.Tech - Electronic Systems Engineering
Indian Institute Of Science
Bangalore 05.2015 - 06.2017
Bachelor of Engineering - Electronics And Communications Engineering
CMR Institute Of Technology
Bangalore 05.2009 - 07.2013
Skills
EDA Tools : NC Verilog, Spy Glass Lint, IRUN, Xilinx Plan Ahead, Cadence Virtuoso, VCS-DVE
Languages : C, Verilog, System Verilog, VHDL, Python, MATLAB
Achievements & Co-Curricular
- Secured 1st position in college in the academic year 2010-2011 (2nd year of BE).
- Awarded scholarship by Indian Air Force in 2009 for academic achievements in AISSCE.
- Recipient of Defence Scholarship from Department of Technical Education, Government of Karnataka 2009-2013.
- Represented Bangalore region in the 39th KVS National Sports Meet in Badminton.
- Lead sports and games organizer during Potluck 2015 at IISc.
- Hobbies include cricket, badminton, football, gymming, swimming.
References
Prabhakar T V Senior Scientific officer,
Department of Electronics Systems Engineering,
Indian Institute of Science, Bangalore-560012
Email: tvprabs@dese.iisc.ernet.in
Timeline
Senior Design Engineer
Synaptics Incorporated
03.2023 - Current
Senior Lead Engineer
Qualcomm
09.2019 - 02.2023
ASIC Design Engineer 2
Juniper Networks
07.2017 - 09.2019
M.Tech - Electronic Systems Engineering
Indian Institute Of Science
05.2015 - 06.2017
Bachelor of Engineering - Electronics And Communications Engineering
CMR Institute Of Technology
05.2009 - 07.2013
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