VIDUSHI BAJPAI
Verification Engineer
Hyderabad,Telangana
Summary
Design Verification Engineer with over 3 years of successful experience in handling SV and UVM based verification environments for complex designs. Collaborated with design team members to effectively test, verify and debug DUT for successful tapeout including closure on coverage metrics. Hands-on experience in bringing up Palladium environment using Perl and Tcl Scripting. Considered hardworking, punctual and strongly driven.
Overview
3
3
Certifications
6
6
years of post-secondary education
4
4
years of professional experience
Work History
Design Verification Engineer
Blaize
Hyderabad, Telangana
07.2018 - Current
- Working closely with RTL designers to specify, develop and debug constrained-random and directed testcases towards coverage driven verification closure
- Development and implementation of verification testbenches, testbench components including stimulus drivers, monitors and checkers and bus-functional models in SystemVerilog
- Develop, simulate and debug directed and random stimulus tests
- Develop and analyze assertions and coverage terms. Participated in technical reviews of the specifications, design and test plans.
- Bring up of ICE and ixcom flow in Palladium and handling database
Intern
Synopsys
Hyderabad, Telangana
07.2017 - 06.2018
- Verdi Exclusions: Understanding and Analysis of Exclusions
- Benchmark and Regression Testing: Converting Spurious test cases to .csh, .cov and .vgt format and testing using ts.verify. Developed MX Brittle Test Cases to Self-Checking
Education
Master of Technology - Integrated Circuit Technology
University of Hyderabad
Hyderabad 07.2016 - 07.2018
Bachelor of Technology - Electronics And Communications Engineering
Krishna Institute of Engineering & Technology
Ghaziabad 08.2012 - 07.2016
Skills
Palladium
Accomplishments
- Awarded with the Above and Beyond for contributions to Multiple ULT Development and Collaboration.
- Awarded with the Scholarship worth 4 lac from Govt of India.
- Promoted to Design Verification Engineer II within 9 months.
Certification
Silver Certification in DSS, DTS and TSI for 6 months, BSNL- [2014-2015]
Timeline
Design Verification Engineer
Blaize
07.2018 - Current
Intern
Synopsys
07.2017 - 06.2018
Master of Technology - Integrated Circuit Technology
University of Hyderabad
07.2016 - 07.2018
Bachelor of Technology - Electronics And Communications Engineering
Krishna Institute of Engineering & Technology
08.2012 - 07.2016
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