ABHINAV LOKA
Design Verification Engineer
Summary
Dynamic FPGA professional specializing in digital design, VHDL/Verilog coding, and hardware simulation, with a proven ability to deliver efficient, high-performance solutions that adapt seamlessly to evolving project requirements. Recognized for a strong commitment to collaboration and achieving impactful results within team settings. Expertise in problem-solving and innovation shines in complex technical environments, driving projects forward with creativity and precision. A passion for excellence ensures the delivery of cutting-edge FPGA solutions that meet and exceed industry standards.
Overview
4
4
years of professional experience
1
1
Certificate
3
3
Languages
Work History
Design Engineer
QI CAP Markets LLP
07.2022 - Current
- Reduced debugging time for complex designs through meticulous test planning and execution.
- Participated in regular design reviews with key stakeholders to gather feedback and make necessary adjustments throughout the development process.
- Increased system performance through meticulous timing analysis and constraint adjustments.
- Collaborated with cross-functional teams to ensure seamless integration of engineering designs into final products.
Verification Engineer Intern
QI-CAP Markets LLP
01.2022 - 06.2022
- Implemented automated testing tools, optimizing resource utilization and minimizing human error risks in the verification process.
- Demonstrated adaptability in a fast-paced work environment by quickly learning new tools and techniques as required for specific project needs.
- Improved system functionality by identifying and addressing design weaknesses through comprehensive testing methods.
- Expedited debugging processes through meticulous log analysis, reducing overall project timelines.
- Optimized FPGA designs with thorough verification, resulting in improved system performance.
- Streamlined verification methodologies, enabling faster completion of projects while maintaining accuracy standards.
Education
Dual Degree(B.Tech + MBA) - ECE
JNTHU College of Engineering
Hyderabad, India 04.2001 -
Intermediate - 12th Class
Narayana Junior College
Hyderabad, India04-2010
SSC - 10th Class
Vijay High School
Armoor03-2008
Skills
Verilog
undefinedCertification
Advanced VLSI Design and Verification Course - Maven Silicon [Aug 2021 - June 2022]
Accomplishments
- Secured GATE AIR-1909 in 2019.
- Volunteered a workshop on 'Avionics Systems in Modern Aircraft' organized by the alumni of JNTUHCEH in association with The Aeronautical Society of India, Hyderabad Chapter.
- Received certificate of appreciation from District Collector for being a 'Webcasting Volunteer' in the General Elections – 2014.
Timeline
Design Engineer
QI CAP Markets LLP
07.2022 - Current
Advanced VLSI Design and Verification Course - Maven Silicon [Aug 2021 - June 2022]
06-2022
Verification Engineer Intern
QI-CAP Markets LLP
01.2022 - 06.2022
Dual Degree(B.Tech + MBA) - ECE
JNTHU College of Engineering
04.2001 -
Intermediate - 12th Class
Narayana Junior College
SSC - 10th Class
Vijay High School
Work Availability
monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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LANGUAGE SKILLS
English: Professional Working Proficiency
Telugu: Native or Bilingual Proficiency
Hindi: Limited Working Proficiency
BEHAVIORAL SKILLS
Well Organized
Stickler
SUBJECT KNOWLEDGE
- Digital Electronics
- RTL Coding
- Code Coverage
- Static Timing Analysis
- FPGA
SOFT SKILLS
- Leadership: I had been in the role of 'Class Representative' for three years during under graduation.
- Teaching: I helped a few Junior college students, with their academics as a private tutor.
BEHAVIORAL SKILLS
Well Organized
Stickler
Hobbies
Cricket,Gardening,Cooking,DIY projects,Long drives
Disclaimer
I hereby confirm that the information flourished above is true to the best of my knowledge. Date: Armoor, Telangana (ABHINAV LOKA)
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