Akash Jain

Key member of PL/MAC PCIe Gen5 functional verification IP, in a team of 8 verification engineers

• Verified several key Physical Layer features of PCIe Gen5 design in both Root Port and End Point mode
• Planned, strategized and performed end-to-end verification of features like - Equalization, Low Power, Error Injection, Polling Compliance
• Worked closely with our internal stakeholders like Transaction Layer team, cluster team, full chip team to bring-up PCIe design on their setup.
• Planned feature deliverables, defined testplans along with coverage requirements, and developed functional verification strategies.
• Implemented stimulus, tests and checkers as part of feature verification
• Collaborated with the design team to analyze and cover holes for code and functional coverage
• Debugged and fixed several regression failure throughout the course of the project.
• Mentored lateral hires and college graduates with my guidance and technical skills to make them self reliant.

Post Silicon Hardware Validation of PCIe Gen5 design in End Point mode

• Investigated and defined testplan to verify each PL/DL feature on silicon
• Developed scripts to inject stimulus and verified results through register dumps
• Worked with FW teams to bring-up tests that require FW interactions.
• Collaborated with the serdes team to resolve interoperability issues with various hosts.
• Leveraged exerciser machine to inject and verify various error scenarios.

Part of a team responsible for IP verification of USB3.1 device controller IP

• Collaborated with team members, in a team of 6 engineers, in developing USB3.1 device controller testbench.
• Verified polling, recovery, hot reset handshake requirements.
• Verified LL/MAC recoverable and non-recoverable critical error scenarios
• Closely worked with Mentor Graphics to resolve issues seen in their USB3.1 VIP, used in the testbench
• Worked in developing LL monitor and scoreboard.

Part of a team responsible for verifying Bluetooth Low Energy (BLE) 4.2 compliant IP.

• Coded assertions for checking connection interval of multiple connections which is very critical in sustaining a connection in BLE.
• Owned Mode Transition (MT) block verification for BLE4.2 compliant IP.
• Power Aware (PA) verification: Aligned the PA infrastructure with the new power optimized design
  for the Bluetooth Low Energy 4.2 compliant IP in PSoC6.

Conducted tutorial sessions related to CMOS circuit analysis for over 90 students