Ameya Deshpande
DMS Verification Engineer
Bengaluru
Summary
DMS Design Verification Engineer with expertise in mixed-signal and high-speed digital verification. Experienced in UVM testbench architecture, PLL/DCO modeling, noise validation, and block-to-SoC integration, with proven coverage closure and published work at DVCON 2025.
Overview
4
4
years of professional experience
Work History
DMS Verification Engineer
Analog Devices
06.2024 - Current
- Currently leading the verification of the RX sampler, TIA, and high-speed digital blocks of an ATE chip, focusing on functional and code coverage, and also supporting GLS debug for the same.
- Led end-to-end verification of a DPLL; achieved 99.7% coverage with 141+ testcases across 7 modes, including RTL and full-chip GLS.
- Developed advanced noise/jitter injection infrastructure with RNM-based modeling and MATLAB-driven noise profiles for realistic verification.
- Drove SoC-level integration and debug for the DPLL block ; raised and resolved over 100 issues to improve silicon readiness and design robustness.
- Published a paper at DVCON 2025 on reusable mixed-signal UVM checkers methodology.
Digital Verification Intern (Industrial Converters)
Analog Devices India Private Limited
06.2023 - Current
- FFT analysis of the ADC output using windowing in different signal paths.
- Writing testbenches for computing SNR in different signal paths and windows.
- Post-processing of the regression results with python.
- Skills: UVM, SystemVerilog, Verilog, Python(basic)
GET (Graduate Engineer Trainee)
Schneider Electric India Private Limited
10.2021 - 05.2022
- Distribution Transformer monitoring system (DTMS) and Sensor testing.
- EMI/EMC testing of Prepaid Electricity meters.
Education
M.Tech - Microelectronics and VLSI Design
Indian Institute of Technology, Ropar
Ropar, India01.2024
Bachelor of Technology - Surathkal
National Institute of Technology Karnataka
Mangalore, India01.2021
Skills
C, Verilog, SystemVerilog, UVM
Cadence Virtuoso,
Cadence Xcelium, SimVision
Matlab and Simulink
Constraint random verification
Verification planning
Code coverage analysis
Testbench development
UVM methodology
Functional coverage
Assertion-based verification
Timeline
DMS Verification Engineer
Analog Devices
06.2024 - Current
Digital Verification Intern (Industrial Converters)
Analog Devices India Private Limited
06.2023 - Current
GET (Graduate Engineer Trainee)
Schneider Electric India Private Limited
10.2021 - 05.2022
M.Tech - Microelectronics and VLSI Design
Indian Institute of Technology, Ropar
Bachelor of Technology - Surathkal
National Institute of Technology Karnataka
Key Courses Taken
- Mtech VLSI: Mixed-Signal IC Design, CMOS Analog IC Design, Digital IC Design, Broadband Communication circuit design, Nanoscale MOSFETs, Circuit Simulation Lab, Advanced Computer Architecture.
- BTech EEE: VLSI CAD, Logic Synthesis techniques, VLSI Design, Digital System Design
Positions of Responsibility
- Teaching Assistant: Analog Circuits Lab, Under Dr. Mahendra Sakare Aug. 2022 - Dec.2022
- GET (Schneider Electric): Overseeing a team of 2 JET’s for prepaid meter testing. Oct. 2021 - Feb.2022