SUVOJIT GHOSH
Bangalore
Summary
Experienced Design Verification Engineer skilled in UVM, SystemVerilog, and test plan development. Proficient at issue resolution and cross-functional collaboration to ensure high-quality products. Adept with EDA tools and committed to optimizing verification for product reliability. Seeking dynamic engineering roles to apply expertise.
Overview
1
1
year of professional experience
Work History
Design Verification Engineer
Chipex Technologies Pvt Ltd
10.2023 - Current
- Leading Design Verification team.
- Working on verification for MIPI D-PHY protocol.
- Developing and executing comprehensive test plans for ongoing project design, employing advanced verification methodologies such as UVM and SystemVerilog to ensure the functionality and reliability of complex digital circuits
- Python Scripting for automating UVM testbench environment
- Collaborating closely with design teams to identify and resolve design issues, ensuring error-free chip designs and contributing to on-time project deliveries
- Utilized industry-standard EDA tools and simulators to simulate and verify digital designs, contributing to the validation and improvement of the product's performance
- Actively participated in cross-functional teams, contributing to the enhancement of verification processes and product reliability, while also mentoring and training junior engineers in verification methodologies and best practices.
Graduate Intern
Intel Technology India Pvt Ltd
09.2022 - 05.2023
- SoC pre-Silicon verification of the latest set of cutting-edge Xeon Server processor.
- Designed and developed verification environments using industry-standard methodologies UVM & SystemVerilog.
- Collaborated with cross-functional teams to define verification strategies, goals, and scope for complex SoC projects.
- Developed and executed verification plans for digital designs, ensuring functional correctness, performance, and compliance with specifications.
- Utilized advanced verification techniques such as constrained random testing, coverage-driven verification, and assertion-based verification to achieve comprehensive coverage metrics.
- Utilized Toggle coverage analysis of Signals in SoC to ensure comprehensive testing and identify areas of improvement.
- Implemented and maintained regression testing infrastructure (Venus Granite Tool), resulting in improved efficiency and design reliability.
- Conducted debug analysis and worked closely with design teams to resolve issues and ensure design correctness using Synopsys Verdi (waveform view) and post regression reports (log files generated).
- Assisted the verification team in test planning, testbench development, and simulation activities.
- Work closely with RTL team to implement the changes in the validation plan.
- Contributed to the development of verification documentation, ensuring clear communication of verification strategies and results.
- Actively engaged in professional development, attending industry conferences and staying up-to-date with the latest trends in SoC verification.
Education
Master of Science - VLSI Design
Vellore Institute of Technology
Vellore07.2023
Skills
- HDL- Verilog, SystemVerilog, UVM
- Scripting Languages- Python, Perl, TcL
- EDA Tools- Intel Quartus Prime, Mentor Graphics ModelSim, Mentor Graphics QuestaSim, Cadence SimVision, Synopsys VCS, Synopsys Verdi, Venus Granite Tool, PrimeTime, Design Compiler, IC Compiler, Cadence Virtuoso
- Operating System- Linux, Windows
- Version Control Tool- git
- Hands on Experience on ASIC Design & FPGA Design
- Strong debugging skills and proficiency in Verilog, SystemVerilog, SVA, UVM
Projects
1. Title- Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator.
(February 2022 - June 2022)
- EDA Tool- Cadence Virtuoso
- Description- Presented a cross-coupled low power double tail comparator circuit which reduced the power consumption to 14.8% from the conventional Comparator circuit.
2. Title- Verification of Synchronous FIFO using UVM
(March 2022 - April 2022)
- EDA Tool- Mentor Graphics QuestaSim
- Description- Prepared verification plan, developed UVM based testbench code for Synchronous FIFO & achieved 100% coverage.
3. Title- ASIC Design of 8 Bit ALU using 14nm FinFET Technology.
(February 2022 - June 2022)
- EDA Tool- Synopsys VCS, PrimeTime, IC Compiler II
- Description- RTL to GDSII ASIC Design flow was performed on the 8-bit ALU design.
4. Title- Bowling Game Score Keeper in FPGA.
(January 2022- January 2022)
- EDA Tool- Intel Quartus Prime 18.1 Lite, Mentor Graphics ModelSim, ALTERA Cyclone IV EP4CE10 FPGA Kit.
- Description- Design of the digital system to keep score for a bowling game was implemented using Verilog HDL.
Achievements & Certifications
1. Qualified GATE in EC in 2020 & 2021 with 93 and 95 percentiles respectively.
2. Verification Using SystemVerilog from Udemy in August 2023.
3. Concepts of Static Timing Analysis from Udemy in January 2022.
4. Vocational training of two weeks on Advanced Telecom at CTTC, Kolkata, Bharat Sanchar Nigam Limited (BSNL).
5. Participated on Three Day Online Workshop on SoC Design Using Open POWER Cores organized by VIT in collaboration with IBM in 2022.
6. Participated on Image Processing Workshop Organized by ROBO School at Jadavpur University in 2015.
7. Represented School Basketball team in CBSE Inter School Sports and Games competition 2010-2011 recognized Ministry of Youth Affairs & Sports.
Declaration
I hereby declare that all the information given above is true to the best of my knowledge.
Date- 25-12-2023
Place- Bangalore, India
Timeline
Design Verification Engineer
Chipex Technologies Pvt Ltd
10.2023 - Current
Graduate Intern
Intel Technology India Pvt Ltd
09.2022 - 05.2023
Master of Science - VLSI Design
Vellore Institute of Technology
Similar Profiles
Venkata Nagaraju InakolluVenkata Nagaraju Inakollu
Technical Lead(System Design) at Relysys Technologies Pvt Ltd (now Invendis Technologies pvt ltd)Technical Lead(System Design) at Relysys Technologies Pvt Ltd (now Invendis Technologies pvt ltd)
S ChetanS Chetan
Assistant Manager - Finance at ANIMALL TECHNOLOGIES PVT LTD, Technologies Pvt LtdAssistant Manager - Finance at ANIMALL TECHNOLOGIES PVT LTD, Technologies Pvt Ltd
Shweta SinghShweta Singh
Support Engineer-IT at I-Telemetry Technologies Pvt. Ltd. (Subsidiary of Aaxis Nano Technologies Pvt. Ltd.)Support Engineer-IT at I-Telemetry Technologies Pvt. Ltd. (Subsidiary of Aaxis Nano Technologies Pvt. Ltd.)
Sijith VJSijith VJ
Principal Software Engineer at OraclePrincipal Software Engineer at Oracle
Sreeram TRSreeram TR
Catalog Manager at AmazonCatalog Manager at Amazon