Ishan Banerjee
Bangalore
Summary
Detail oriented VLSI engineer with 3 year of experience in designing and verifying. Proficient in the SV, UVM and Verilog. Adept to industry standard tool likes Synopsys. Experience of working in the formal verification in both the SoC and the IP level.
Overview
3
3
years of professional experience
Work History
Design Verification Engineer
Insemi Tech. Pvt. Services Ltd.
Bangalore
07.2021 - Current
- Working on the ip camera formal verification. Do all the connectivity check like mem_svs, mem_acc & mem_clamp.
- Checking the reverse connectivity check. Comparing the connections with the legacy projects.
- Doing Formal ahb bus certification checks and formal reset checks.
- checking the fuse connectivity, interrupt connectivity and non functional port checks using the vcs formal tool.
- Did the SoC Pipeline verification and Pakage verification.
- Good understanding of the integration activity. Creation of Pre compiled RTL ,arm address file generation and novas generation.
- implementing the toggle coverage(generating the exclusions and the vdb file generation),functional coverage at the SoC level.
- Generating the assertion binding.
- Setting the TPM(Test Plan Management) for the team.
Education
M.Tech - Electronics Design Technology
Tezpur University
Tezpur,Assam10-2020
B.Tech - Electrical & Electronics
West Bengal University of Technology
Kolkata04-2015
Skills
- Systemverilog
- Verilog
- UVM
- Python
- Perl
Languages
Bengali
First Language
English
Upper Intermediate (B2)
B2
Hindi
Intermediate (B1)
B1
Websites
Timeline
Design Verification Engineer
Insemi Tech. Pvt. Services Ltd.
07.2021 - Current
M.Tech - Electronics Design Technology
Tezpur University
B.Tech - Electrical & Electronics
West Bengal University of Technology
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