Himanshu Bhushan

Design Verification Engineer | Intel Test Card Projects

Project 1. USB 3.2 Controller with Tunneling 2.0 (USB4 v2.0)

Key Responsibilities:

• Authored and executed UVM test cases to verify the initial host-to-controller connectivity and LTSSM (Link Training and Status State Machine) transitions, ensuring a stable link-up for Tunnelling 2.0 environments.
• Developed targeted verification test cases for Bulk, Interrupt, Control, and Isochronous transfers, validating the controller's ability to prioritise and manage diverse data streams.
• Developed complex test cases to validate the Stream Protocol within bulk transfers, ensuring the controller could manage multiple high-speed data streams without loss of synchronisation.
• Designed complex error injection test cases (CRC errors, protocol/link-layer mismatches, and timeout scenarios) to verify the controller’s recovery logic and host-side error reporting within the 80 Gbps USB4 v2.0 fabric.
• Led the regression cleanup phase, debugging complex failures using Synopsys Verdi to achieve a 'clean' regression status.
• Developed a script to automate the categorisation of the regression results using Perl.

Methodologies: UVM Test Case Development (System Verilog), Constrained-Random Testing.

Protocols: Tunnelling 2.0 (USB4 v2.0), USB 3.2.

Tools: Synopsys VCS, Verdi, and DVE.

Project 2: OSEA (Open System Extension Architecture) Test Card.

• Modernised the legacy test suite by developing and integrating new checkers to validate LTSSM transitions and LFPS (Low Frequency Periodic Signalling).
• Updated existing test cases with enhanced checkers for Bulk, Interrupt, and Control transfers.
• Helped to debug the existing Perl-based script for running regressions for the enhanced test cases.

Methodologies: OVM, SystemVerilog, and Checker/Monitor Development.

Protocols: USB 3.2 Gen 1/Gen 2 (Dual-Lane).

Tools: Synopsys VCS, Verdi.

Design Verification Engineer | Intel Automotive (SiMO Project)

Key Responsibilities

• Developed a high-performance Proxy CPU by configuring and deploying AXI Verification IP (VIP) as an AXI Master; this replaced the full processor model in the ACU SoC environment to bypass CPU fetch/decode cycles and significantly accelerate simulation turnaround time.
• Utilised the Proxy CPU to drive high-bandwidth directed and random stimuli into the AXI4/AXI-Lite fabric.
• Modified Makefile scripts to seamlessly integrate the Proxy CPU's UVM testbench into the top-level SoC simulation flow

Methodologies: UVM SystemVerilog

Protocols: AMBA AXI

Tools: Synopsys VCS, Verdi.

Projects worked on:

Router 1x3 – RTL design and Verification

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1, and channel2.

Responsibilities:

· Architected the block-level structure for the design

· Implemented RTL using Verilog HDL.

· Architected the class-based verification environment using UVM (System Verilog)

· Verified the RTL model using the developed test bench.

· Generated functional and code coverage for the RTL verification sign-off

· Synthesized the design.

HDL: Verilog

Methodologies: UVM (System Verilog)

EDA Tools: Questasim and ISE