Yashwanth Mokkapati
Bengaluru
Summary
Dynamic Design Verification Engineer with proven expertise at Microchip Technologies, specializing in system reliability and functional verification. Proficient in SystemVerilog and Perl, I enhanced testing efficiency through automation. Adept at leading engineering changes and optimizing embedded systems, I bring strong analytical skills and a commitment to excellence in high-stakes environments.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Design Verification Engineer
Microchip Technologies
06.2023 - Current
- Verified Event Controllers, ensuring accurate functionality and performance within embedded systems, with a focus on system reliability and event-driven processes.
- Conducted Verification of Analog Modules with calibration features, validating their precision and functionality in real-world applications.
- Applied intermediate proficiency in Perl scripting to automate verification processes, enhancing testing efficiency and reducing manual errors.
- Led Engineering Change Orders (ECOs) for minor revisions, ensuring effective management of product updates and design improvements.
- Applied in-depth knowledge of AVR and PIC architecture for system optimization.
- Knowledgeable about ARM Cortex-M0+ based system verification in a C-SV setting, with an emphasis on memory subsystems and fast peripherals.
- Verified NVM Controller macros, paying particular attention to CALOTP persistence, In-System Self-Programming, and 16-region memory protection logic to guarantee that crucial application data endures chip-erase sequences.
- Experienced in testing chip-level designs utilising AMBA APB and AHB-Lite, as well as a thorough understanding of on-chip bus topologies.
Intern
Microchip Technologies
01.2023 - 06.2023
- Functional Verification of 8-bit AVR Microcontroller Macros i.e., Oscillator Controllers in an ASM test environment has been done.
- Familiar with the intricacies of AVR microcontroller architecture.
- Gained comprehensive knowledge of ASM-SV test environment.
Education
B.Tech - Electronics and Communication Engineering
Amrita Vishwa Vidyapeetham
Bengaluru, KA2023
Junior College - MPC
Narayana Junior College
Hyderabad2019
High School -
Narayana Olympiad School
Hyderabad2017
Skills
- SystemVerilog
- C
- Perl
- TCL
- Cadence SimVision
- Functional Verification
Certification
- TCL Workshop: From Introduction to Advanced Scripting Techniques in Design and Synthesis by VLSD (Project Repo: https://github.com/binocroc/TCLWorkshop)
- Verilog/SystemVerilog for Design and Synthesis by Sutherland HDL
- SystemVerilog Assertions for Design Engineers and Verification Engineers by Sutherland HDL
Hobbies and interests
- Badminton
- Carnatic Music
Timeline
Design Verification Engineer
Microchip Technologies
06.2023 - Current
Intern
Microchip Technologies
01.2023 - 06.2023
B.Tech - Electronics and Communication Engineering
Amrita Vishwa Vidyapeetham
Junior College - MPC
Narayana Junior College
High School -
Narayana Olympiad School