KARTHEEK GILAKATHULA
Hyderabad
Summary
Design Verification Engineer with hands-on experience in RTL design and verification using Verilog, SystemVerilog, and UVM. Proficient in building and debugging UVM-based environments, automating verification flows using Tcl and Python, and validating designs on Xilinx FPGA architectures. Skilled in AXI4 protocol verification, coverage analysis, and FPGA implementation flows. Proven ability to work on internal and client-modeled IP projects with ownership and accountability.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Design Verification Engineer
InnovCentric Pvt. Ltd.
Hyderabad
02.2023 - 03.2025
- Developed and verified RTL modules for internal IPs modeled on Tier-1 client specs.
- Built UVM-based verification environments: agents, monitors, scoreboards, sequencers.
- Verified AXI4-based master/slave communication, handling burst types and data integrity.
- Automated simulations and regressions using Tcl and Python scripting.
- Validated designs on Xilinx FPGA boards (Zynq family) using Vivado and Chipscope.
- Debugged complex signal interactions using QuestaSim and Verdi.
- Key Contributions: Reduced regression run-time by ~25% with efficient Tcl scripting.
- Created reusable UVCs for AXI4, adopted in multiple IP-level verifications.
- Participated in PCIe training simulation, modeling LTSSM and TLP flow basics.
Intern - Digital Design & Verification
Sumedha IT
Hyderabad
07.2022 - 01.2023
- Designed basic Verilog RTL modules and testbenches for UART, counters, FSMs.
- Gained foundational experience in UVM methodology and coverage-driven verification.
- Practiced simulation scripting with Tcl and Python; introduced to FPGA synthesis flow.
Education
Bachelor of Engineering - Electrical and Electronics Engineering
Vasavi College of Engineering
Hyderabad08-2022
Skills
- Verilog
- SystemVerilog
- VHDL
- Python
- Tcl
- C
- UVM
- RTL Design
- Functional & Code Coverage
- Assertions (SVA)
- QuestaSim
- Vivado
- Verdi
- Git
- Xilinx Zynq
- ILA
- Timing Constraints
- AXI4
- PCIe
- UART
- SPI
- Linux
- Assertion-based verification
Certification
- Advanced Design Verification with UVM, 6-Months Certification
- Xilinx FPGA Architecture and Design Flow, In-house Project Exposure
- Scripting for verification automation (Tcl/Python), project-based
Projects
AXI4 UVM Testbench, Developed a full-featured UVM testbench for AXI4-compliant IP. Implemented agents, sequencers, monitors, and scoreboards. Achieved 100% functional and 95% code coverage in regressions.
PCIe LTSSM Simulation (Training), Modeled PCIe link states using SystemVerilog testbench. Simulated basic packet transfers and TLPs for educational purposes.
Timeline
Design Verification Engineer
InnovCentric Pvt. Ltd.
02.2023 - 03.2025
Intern - Digital Design & Verification
Sumedha IT
07.2022 - 01.2023
Bachelor of Engineering - Electrical and Electronics Engineering
Vasavi College of Engineering