
Professional engineer with experience in design verification, specializing in digital and analog circuit validation. Skilled in using advanced verification methodologies, debugging, and simulation tools. Strong focus on team collaboration and delivering reliable results, adaptable to changing project needs. Known for keen problem-solving abilities and effective communication with cross-functional teams.
Verilog
System Verilog
UVM
Questasim
Modelsim
Verdi
Linux
Windows
APB
AHB
UVM methodology
Functional coverage