Mrunali Choudhari
Bangalore
Summary
Functional Verification Engineer with 3 years of experience in ASIC/IP verification using SystemVerilog and UVM. Experienced in developing reusable verification environments, writing constrained-random and directed testcases, debugging simulation failures, and achieving functional coverage closure. Worked on PCIe Gen4/Gen5, Ethernet MAC, AHB, and APB protocol verification at IP and subsystem levels. Comfortable working with cross-functional design teams to verify complex digital designs and deliver high-quality verification before tape-out.
Overview
1
1
Certification
4
4
years of professional experience
Work History
Design Verification Engineer
SpanIdea Systems
07.2025 - 12.2025
- Verified PCIe Gen4 subsystem integrated with Synopsys PCIe Controller.
- Developed and executed UVM test cases, enhancing subsystem-level verification efficiency.
- Verified PCIe LTSSM transitions, link training, and low-power states (L0s and L1).
- Worked on constrained-random and directed verification to validate protocol functionality.
- Debugged functional failures using simulation waveforms and protocol logs.
- Ported and integrated existing verification environments and test cases, improving consistency across projects.
- Collaborated with RTL and architecture teams to resolve design issues.
- Supported regression execution and conducted functional coverage analysis to ensure comprehensive validation.
Design Verification Engineer
App-Ex Semiconductor
03.2024 - 04.2025
- Created UVM test cases to effectively verify LTSSM states, polling, and configuration, ensuring compliance with design requirements.
- Developed comprehensive verification plans aligned with design specifications to ensure thorough validation.
- Performed constrained-random verification and protocol compliance checks.
- Executed regression tests and contributed to coverage closure activities to enhance verification completeness.
- Analyzed simulation results and debugged RTL issues using waveforms.
- Worked with design engineers to resolve functional bugs.
Design Verification Engineer
App-Ex Semiconductor
07.2023 - 02.2024
- Created directed and constrained-random testcases to ensure comprehensive validation of design specifications.
- Implemented functional coverage for protocol features to identify verification gaps and improve test accuracy.
- Developed reusable UVM verification components to enhance modularity and efficiency of verification processes.
- Executed verification of error injection and packet handling scenarios during testing.
- Debugged simulation failures and supported regression testing.
Design Verification Engineer
Atria Logic Pvt Ltd
12.2022 - 04.2023
- Developed UVM verification environment, enhancing verification process for AHB and APB protocols.
- Implemented functional coverage and protocol assertions.
- Verified read/write transactions, ensuring protocol compliance and functionality.
- Developed directed and constrained-random test cases.
- Executed simulation debugging and regression tests, identifying issues to improve overall design reliability.
Advanced VLSI Design and Verification
Maven Silicon VLSI Design
04.2022 - 11.2022
Education
Advanced VLSI Design and Verification -
Maven Silicon VLSI Design
Bangalore11-2022
B.E - Electrical Engineering
Rajiv Gandhi College of Engineering And Research
Nagpur, Maharashtra06-2020
HSC -
Dinanath High School & Jr College
01-2016
Skills
- System Verilog
- Verilog
- Linux
- UVM
- Constrained Random Verification
- Coverage Driven Verification
- PCIe Gen4/Gen5
- Ethernet
- AHB
- APB
- Testbench Development
- Driver
- Monitor
- Scoreboard
- Functional Coverage
- Assertions
- VCS
- Questa Sim
- EDA
Certification
Advanced VLSI Design and Verification, Maven Silicon VLSI Design, Bangalore, 04/01/22, 11/30/22
Timeline
Design Verification Engineer
SpanIdea Systems
07.2025 - 12.2025
Design Verification Engineer
App-Ex Semiconductor
03.2024 - 04.2025
Design Verification Engineer
App-Ex Semiconductor
07.2023 - 02.2024
Design Verification Engineer
Atria Logic Pvt Ltd
12.2022 - 04.2023
Advanced VLSI Design and Verification
Maven Silicon VLSI Design
04.2022 - 11.2022
Advanced VLSI Design and Verification -
Maven Silicon VLSI Design
B.E - Electrical Engineering
Rajiv Gandhi College of Engineering And Research
HSC -
Dinanath High School & Jr College