Kuber Nath Derasari

Highly motivated Design Verification Engineer with 3 years of experience in rigorously verifying complex digital designs. Proven ability to identify and debug issues, contributing to the discovery and resolution of 35 bugs in a recent project. Adept at crafting and executing verification plans using UVM and leveraging SystemVerilog assertions for comprehensive coverage. Possesses strong collaboration skills and works effectively with design and architecture teams to ensure design intent is met.

Implementation of 32 bit Pipelined RISC Processor - VLSI ARCHITECTURE 

• RISC Machine of 5 stages was implemented
• Data Hazards and Control Hazards were eliminated using Hazard Detection Unit Direct Mapped
• Cache was implement along with Main memory in Memory Stage

 A High-Speed Power Efficient Voltage Level Shifter - VLSI Design

• High speed and power efficient voltage Level Shifter was designed in Cadence
• Layout was designed for the same
• DRC and LVS was performed to validate the layout and design

 Clock Domain Crossing (CDC) Verification

• Developed SystemVerilog assertions to verify proper synchronization between signals crossing different clock domains
• Used assertions to check for metastability issues, glitches, and data validity during transfers.