Summary
Overview
Work History
Education
Skills
Accomplishments
Personal Information
Languages
Websites
Timeline
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ARPIT GUPTA

Delhi

Summary

  • Working as a Principal Design Verification Engineer in NXP Semiconductors.
  • Having more than 8.5+ Years of experience in VLSI Industry.
  • Leading the Complete End to end verification of Security SS .
  • Having Patent on Security*Safety Aspect.
  • Leading the VDK methodology which enables customers to start building their SW even before chip tapeout.
  • Good know how of ARM Based Cores .
  • Expertise in doing the complete verification starting from Planning (Architectural Discussion) to Tapeout

Overview

9
9
years of professional experience

Work History

Principal Design Verification Engineer

NXP Semiconductors
Noida
09.2019 - Current
  • To Deliver bug-free Security / Platform SS / VDK domains.
  • Led the complete verification process, overseeing all aspects from initial architectural discussions to final Chip Tapeout.
  • Leading / Building the team for Security Verif Activities.
  • Responsible for VDK / Platform activities . VDK enables
    customers to start Building their SW even before Chip Tapeout.
  • Implemented improved techniques for security verification to enhance quality and signoff checks.
  • Earlier Worked on DSP SS , SDADC , MU etc.
  • Managed and optimized makeflow activities for RISCV Architecture.
  • Defined Test Suite and Overall Planning for system level scenarios at Simulation level and providing inputs to Emulation team.
  • Setting up the GLS level environments.
  • Closure of Coverage.

Design Verification

Analog Devices
05.2019 - 09.2019
  • Successfully established the GLS and PTE simulations flow.

Design Verification

ST Microelectronics
07.2017 - 04.2019
  • Responsible for meticulously verifying the functionality of various modules including CGM, SSCM, SRAM to maintain high standards of operation.
  • Conducted RTL level simulations as well as timing and non-timing GLS.
  • Performed system level scenario verification.
  • Lead the HSM SS verification .
  • Demonstrated proficiency in carrying out complete testing procedures.

Design Verification

Qualcomm India Onsite
11.2015 - 06.2017
  • Conducted memory, USB, PCIE, and low-speed peripheral verification during the early stages.
  • Developed and implemented the entire gate level simulation setup.
  • Done the Design Verification at RTL , Gate Level simulation (Timing and Non timing).

Education

B.Tech (E.C.E) -

Guru Gobind Singh Indraprastha University
01.2015

12th Board -

CBSE
01.2011

10th Board -

CBSE
01.2009

Skills

  • Verilog /System Verilog /UVM
  • AHB / AXI Bus protocols
  • ARM Core Based SOC's
  • Verification planning
  • SVA
  • Little bit of scripting language TCL/ PERL
  • Team Management

Accomplishments

  • Having Patent in Security Domain
  • Published Papers on DSP-SS , Security platforms at various platforms.
  • Won many Spot Awards for Work Recognition

Personal Information

  • Date of Birth: 09/Nov/93
  • Gender: Male
  • Nationality: Indian
  • Marital Status: Married

Languages

Hindi
First Language
English
Upper Intermediate (B2)
B2
Punjabi
Upper Intermediate (B2)
B2

Websites

Timeline

Principal Design Verification Engineer

NXP Semiconductors
09.2019 - Current

Design Verification

Analog Devices
05.2019 - 09.2019

Design Verification

ST Microelectronics
07.2017 - 04.2019

Design Verification

Qualcomm India Onsite
11.2015 - 06.2017

B.Tech (E.C.E) -

Guru Gobind Singh Indraprastha University

12th Board -

CBSE

10th Board -

CBSE

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