ATHIRA V V

Results-driven Design Verification Engineer with expertise in Verilog and System Verilog, honed at UST Global. Successfully developed VIP and implemented functional coverage, enhancing verification efficiency. Proficient in EDA tools like Mentor Questa, while demonstrating strong analytical skills and effective communication in collaborative environments. Have successfully developed comprehensive test plans and driven bug resolution processes to improve product quality. Innovation-driven with ability to solve complex problems efficiently and effectively.

Certified Advanced VLSI Design and Verification Course, 2021, Maven Silicon, Bengaluru

Verilog, System Verilog, UVM, AHB, APB, UART, SPI, Mentor Questa, Model sim

• Verification of Display driver IC (Project name- Talisman) Block : MBIST

Display Driver IC is an integrated circuit chip that controls the switching and display method of LCD and AMOLED Panels. Talisman is a controller Driver IC for active-matrix organic light emitting diode (AMOLED) display. MBIST is a self-testing and repair mechanism which tests the memories through an effective set of algorithms to detect possibly all the faults that could present inside a typical memory cell. As an MBIST Block verification DRI, I understood the project specification, the test plan, and the attribute plan created, VIP development, the reference model checker implemented, the sequence created, attribute and random TCs implemented, updated the coverage collector, debugged regression failures, reported bugs, and verified the MBIST RTL with a UVM test bench using different scenarios like custom pass, custom fail, custom repair pass, and custom repair fail, while closing functional coverage and code coverage with 100%.

• Verification of Display driver IC (Project name- Iris and Pioneer) Block :Temperature controller ,NVM memory and UVM

 Iris and Pioneer has an embedded temperature sensor which detects temperature and an embedded NVM. This is a CMOS OTP device divided into Trim memory block, Main1, Main2, Main3 and Main4 block. As the temperature controller and NVM memory blocks verification DRI, I understood the project specification, created the test plan and attribute plan, developed the VIP, implemented the reference model checker, created the sequence, implemented the attribute and random TCs, updated the coverage collector, debugged regression failures, reported bugs, and verified the temperature controller and NVM RTL with the UVM test bench using different scenarios, closing functional coverage and code coverage with 100%

• Verification of Display driver IC (Project name- Tropica) Block : UVM, Clock_generation and ISM block

Clock_gen generates clock signal that synchronize various operations of the display system and implements clock gating by selectively disabling the clock signal to parts of the circuit that are not in use, thus reducing power consumption .Tropica supports In system MBIST.As Clock_generation and ISM block verification DRI, Understand the project specification, Test plan and attribute plan created, VIP Development, Reference model checker implemented, Sequence created, Attribute and Random TC’s Implemented, Updated the coverage collector, Debugged regression failures and Reported Bugs, Verified the clock_gen and ISM RTL with UVM Test Bench using different scenarios., Closed Functional coverage and code coverage with 100%. 

• AHB to APB Bridge IP Core Verification

The AHB to APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. Read and write transfers on the AHB are converted into equivalent transfers on the APB. Understand the APB/AHB specification document, developed the AHB to APB Bridge Scoreboard, verified the RTL module with the UVM Test Bench using different test scenarios like single read, write, and burst read, write with different burst lengths, debugging test failures, generated functional coverage for the RTL verification, found bugs and reported issues, and documented all verification efforts

• UART IP Core Verification

The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a modem or other external devices, like another computer, using a serial cable and RS-232 protocol. UART takes bytes of data and transmits the individual bits in a sequential fashion At the destination, a second UART re-assembles the bits into complete bytes. As part of this project, I understood the UART IP Core specification and architecture document, defined the Verification Plan and Test Plan, verified the RTL module with a UVM Test Bench using different test scenarios like loopback mode, half-duplex mode, full-duplex mode, verified different interrupts, verified the functionality of the UART in different configurations of the Line Control Register, debugged test failures, generated functional coverage for the RTL verification, found bugs and reported issues, and documented all the verification efforts