Ankur Singhai
Bangalore,,Karnatka
Summary
A systems engineer with over 8 years of experience in the space sector , specializing in LEO satellite imaging payloads design and GEO satellite ground segment operations. Proven expertise in solution architecture, project management, and the development of mission-critical systems, driving innovation and efficiency. Adept at leading cross-functional teams, optimizing hardware and firmware solutions, and ensuring robust project execution. Strong background in systems engineering and design, complemented by a solid foundation in electronics and control systems.
Overview
12
12
years of professional experience
1
1
Certification
Work History
Senior Systems Engineer
KaleidEO Space Systems (A SatSure Co.)
10.2022 - Current
- Successfully led the aerial test campaign to raise the payload's technology readiness level (TRL) to 6
- Managed high-quality documentation to support project requirements (Trade-off studies, V&V, ICDs, CONOPS)
- Lead the design and development of payload electronics system for high swath imaging payload
- Lead the development of drive electronics and control system for the piezo actuator system of the payload
- Lead the firmware and software development of the aerial test imaging payload
Scientist
Indian Space Research Organization
07.2017 - 10.2022
- Ground station manager - Managed the ground station links from 65 antenna terminals for round the clock mission critical operations of 30 geo-stationary and geo-synchronous satellites
- End-to-end engineering to establish new ground segment facilities for satellite operations
- Lead the pre-launch functional checks team of the ground station deployed for the launch missions and manned the Antenna console during critical phases of the launch
- Development, installation and commissioning of in-house developed antenna control system for tracking satellites in the Geo-synchronous orbit
- Team member for the indigenous development of ground segment equipments (SDR based spectrum analyzer, Down converter, Test loop translator)
Design Engineer 2
Advanced Micro Devices (AMD)
08.2013 - 04.2014
- Developed and executed pre-silicon verification test plans for DFT features of the chip, for eg IEEE 1149.1(JTAG), IEEE 1687 and IEEE P1500
- Built test benches for SOC level verification of DFT design blocks and subsystems and carried out tests in a UVM enabled integrated environment consisting of agents, monitors and checkers
- Debugged regression test failures and rectified the issues to achieve desired level of coverage
- Collaborated with DFT and Post Silicon ATE debug teams for generating the required test patterns
Education
M-Tech. - Integrated Electronics & Circuits (VLSI)
Indian Institute of Technology - Delhi
India06-2013
B-Tech. - Electronics & Commuication Engineering
National Institute of Technology- Bhopal
India06-2011
Skills
- EO Systems Engineering
- Technical Systems Analysis
- Satellite Control Operations
- Satellite Ground Segment Development Strategy
- Camera systems AIT
- Electronics System and RTL Design
- High Performance Data Acquisition Systems
- Robotics and Artificial Intelligence
Extra-Curricular Activities
- Robotics: Won 1st prize in Tryst-08, Annual Technical festival of IIT-Delhi.
- Badminton: Represented NIT-Bhopal in national level inter-NIT competition at NIT-Jaipur.
Internship & Projects
1. "Text Recognition based Autonomous Navigation System", DRMZ Tech., Bhopal.
- A dual camera-based navigator equipped with complete on-board processing system.,
- A neural network based approach for text and pattern recognition.
- Provision for remote surveillance and text reader for visually challenged people.
2. Built in Self Test and Repair of Memory (MBIST Controller)
- Runtime fault detection and repair of memory.
- Extensive fault coverage with March B algorithm.
- Use of local optimization and repair most technique for repair action.
Certification
Foundations of Project management - Google
Timeline
Senior Systems Engineer
KaleidEO Space Systems (A SatSure Co.)
10.2022 - Current
Scientist
Indian Space Research Organization
07.2017 - 10.2022
Design Engineer 2
Advanced Micro Devices (AMD)
08.2013 - 04.2014
M-Tech. - Integrated Electronics & Circuits (VLSI)
Indian Institute of Technology - Delhi
B-Tech. - Electronics & Commuication Engineering
National Institute of Technology- Bhopal
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