Anni benitta
Physical Design Engineer
Bangalore
Summary
Accomplished Physical Design Engineer with hands-on experience in RTL to GDS flow implementation. Specializes in floor planning, placement, Clock Tree Synthesis (CTS), routing, and timing convergence using Synopsys tools. Effectively resolves complex physical design challenges while achieving timing and power requirements in advanced technology nodes.
Overview
1
1
Certification
2
2
years of professional experience
Work History
Physical Design Engineer
Smartsoc Solutions
06.2024 - Current
- Developed proficiency in PnR flow and TCL scripting, supporting design optimization
- Assisted in implementing block-level designs, facilitating project execution
- Contributed to physical design tasks, enhancing overall project development
- Collaborated with team members to meet project objectives
- Identified issues and analyzed data to provide solutions
Education
M.Tech - undefined
KCG College of Technology
Chennai, TN05-2016
B.E - undefined
Vins College of Engineering
Nagercoil, TN05-2014
Skills
Physical Design: Floor-planning, Placement, Clock Tree Synthesis (CTS), Routing, DRC/LVS, Timing Convergence, Power Planning, IR Analysis
Operating Systems: Linux, Windows
EDA Tools: ICC2, Fusion Compiler, Innovus, genus, conformal
Design Flow: Complete RTL to GDS implementation, Timing Optimization, Congestion Analysis
Certification
Physical Design Course: STAR VLSI (2023-10 – 2024-05)
Timeline
Physical Design Engineer
Smartsoc Solutions
06.2024 - Current
B.E - undefined
Vins College of Engineering
M.Tech - undefined
KCG College of Technology