Ansh Kumar

FFT pipeline implementation on Xilinx ZCU111 RFSoC using Vivado IP cores

Integrated and verified IP blocks using AXI-Stream interfaces for efficient data flow.

Performed simulation, synthesis, and hardware validation on the RFSoC platform.

Gained hands-on experience with the Vivado Design Suite, including resource utilization analysis and performance tuning.

Strengthened understanding of digital signal processing (DSP) and FPGA-based system design.

• Carried out a project titled Analysis of Transmission Line Characteristics: Terminations, Reflections, and Crosstalk. Conducted experimental analysis of transmission line characteristics, focusing on terminations, reflections, and crosstalk impacts. Built a simple Time-Domain Reflectometry (TDR) setup using basic components to perform signal integrity tests without sophisticated test equipment. Used waveform analysis techniques to access impedance mismatches, propagation delays, and signal degradation, and documented findings.

• Carried out a project titled Design and Develop an Electronic Load Circuit that can be used to test DC power supplies under controlled load conditions. The circuit was initially designed to operate in constant current mode of operation and later enhanced to support constant power operation, all done entirely using analog circuitry.