Ashwin Kondoth

Highly motivated and dedicated Front-end VLSI Engineer with a deep understanding of digital Logic Design and RTL coding and functional testing using Verilog. Eager to contribute to complex IP and SOC verification.

• APB Interfaced SPI Core

Verified an APB based SPI core that enables protocol conversion between APB master and SPI configured as a master, ensuring proper data transfer and sampling from SPI slave device using UVM Testbench., Verified on key building blocks including serial clock generation and baud rate calculator, slave select control, APB slave block and shift registers to support seamless interoperability between APB and SPI buses.

Achieved 100% functional coverage and verified the functionality using assertions for both APB and SPI. 

Language: Verilog, SystemVerilog

Tools: VCS, Questa (Simulation), Synopsis Design Compiler, VC spyglass

Contributions: protocol design and understanding, Verification testing

• AXI-AHB BRIDGE

Verified an AXI to AHB bridge that enables bus protocol conversion between AXI to AHB, ensuring proper read and write operations with wait, no-wait and error states using UVM Testbench. Verified on different burst transfers such as FIXED, INCR and WRAP. 

Achieved 100% functional coverage and verified the functionality using assertions for both AXI and AHB.

Language: Verilog, SystemVerilog

Tools: VCS, Questa (Simulation)

Contributions: protocol understanding, Verification testing

• Playing Badminton
• Organizing things
• Exploring new places
• Learning new skill

Maven Silicon Softech Pvt Ltd (Nov 2025 - Present)

Advanced VLSI Design and Verification Trainee

Completed comprehensive training in Digital Design, Verilog RTL Design, DFT, System Verilog, and UVM methodology, supported by hands-on projects involving RTL development, UVM based verification, assertions, and functional coverage in real-world design scenarios.