JEJU MAHADEV ANANTHA SAI VELCHURI
CHENNAI
Summary
A hardworking and passionate job seeker with strong professional skills, willing to work in a challenging environment, with good knowledge of hardware, software, and effective programming skills, and a successful dependable candidate able to manage multiple priorities with a positive attitude and ready to help the team achieve company goals with a willingness to take on additional responsibilities.
Overview
4
4
years of professional experience
1
1
Certification
Work History
VLSI Design and Verification Trainee
Maven Silicon
Bangalore
03.2022 - Current
- Consistently performed well throughout the course and quickly learned new skills and applied them effectively.
- Achieved a good understanding to make an effective Design, Test Bench, and TB environment for verifying the Design in all corner cases based on required functionality.
Assistant Manager
Saptagiri Grameena Bank
Chennai
07.2021 - Current
- Managed DC-DR activities.
- Created VMs and managed VMWare Database for effective utilization of resources.
- Maintained relationships with Sponsor Bank, ATM/PoS, and CBS Vendors, while performing additional job duties.
Validation Engineer
SoCtronics Technologies Pvt Ltd
Hyderabad
01.2019 - 09.2020
- Post-silicon validation of I2C, SPI, UART, Timer, GPIO, ADC, DAC, etc.,
- Pre-silicon validation of I2C, SPI, UART.
- Automated and replicated latch-up issue (GPIO) using python scripts.
- Involved in debugging USB issues (like Port Detach).
Intern
Veda IIT
Hyderabad
07.2018 - 01.2019
- Trained in Digital electronics concepts.
- Programming Languages: C, Data structures, Perl, and Unix.
- Basic understanding of serial protocols.
Education
Bachelor of Technology - Electronics And Communication Engineering
05.2018
- Final Grade: 80.69%
Skills
- Digital Electronics
- HDL - Verilog
- HVL - System Verilog
- Verification Methodologies - Constraint Random Coverage Driven Verification, Assertion-Based Verification - SVA
- Test Bench Methodology - UVM
- Programming Languages: C, C (OOPs concepts)
- Scripting Language: Perl
- Protocols: I2C, SPI, UART, AHB, AXI
- EDA Tools: Modelsim, Quartus Prime, Questasim
- Operating System: Window, Linux
VLSI Projects
Router 1x3 RTL Design and Verification:
- The router accepts data packets on a single 8 Bit data port and routes them to one of the three destination channels (channel - 0/1/2).
- RTL Design is implemented using Verilog HDL, synthesized the Design, verified the RTL using Verilog Test Bench, and Generated Code coverage report for the Design.
Dual-Port RAM RTL Design and Verification:
- Dual-Port RAM (4096x64) is addressed using 12-bit addresses and data ports each of 64-bit and is constructed using structural modeling.
- Implemented the Design using Verilog HDL, created a Class-based Verification Environment using System Verilog, and verified the Design.
- Synthesized the RTL Design, and generated Functional coverage, and Code coverage reports for the Design.
Certification
- Star of the Month (April, May) during Advanced VLSI Design and Verification Certification Course.
Hobbies
- Listening to music is a stress buster and keeps me enthusiastic all day.
- Cricket is my favorite sport and I enjoy watching it.
Languages
English
Telugu
Hindi
Timeline
VLSI Design and Verification Trainee - Maven Silicon
03.2022 - Current
Assistant Manager - Saptagiri Grameena Bank
07.2021 - Current
Validation Engineer - SoCtronics Technologies Pvt Ltd
01.2019 - 09.2020
Intern - Veda IIT
07.2018 - 01.2019
Sree Vidyanikethan Engineering College - Bachelor of Technology, Electronics And Communication Engineering
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