Ashwin Kulkarni

Project: HSIOWW Design

• Role: Design Engineer
• Tools: Synopsys Core Assembler

Contributed to the HSIOWW design, focusing on the development of various key modules, including:

• APB Bridge Module: Designed with a wait timeout feature to enhance reliability in communication.
• APB-SRAM Converter Module: Facilitated efficient data transfer between APB and SRAM.
• PONSS Bridge Module: Developed both IO Bus and OCP to SRAM conversion logic modules, ensuring seamless data integration.

Additionally, I was involved in:

• PONSS Integration: Implemented PONIP, DESC, ETHUS, and DMA modules using Core Assembler.
• HSIOWW Integration: Utilized Core Assembler for the integration of PONSS, PCIe4, Ethernet XLG, and E32PHY, along with the Glue Top module, all developed in accordance with High-Level Architectural Specifications (HAS).

I also generated memory components using a memory compiler and created wrapper modules to support the integration of sub-blocks within HSIOWW.

This role significantly enhanced my expertise in high-speed interface design and module development, contributing to the overall functionality and performance of the system.

Project: Up-link ORAN Processor Design

Role: Subsystem Designer/Verification Engineer

• Micro-Architecture Understanding: Conducted in-depth micro-architecture analysis of the Up-link ORAN Processor subsystem, ensuring alignment with design specifications and performance targets.
• Physical Uplink (PU) Block Design Updates: Managed design updates for the Physical Uplink Block, performing verification and debugging activities, including the resolution of RTL bugs to enhance subsystem functionality.
• RTL Implementation of Interrupt Controller:Designed and implemented an Interrupt generation module at the IP level, focusing on the integration of Interrupt Status Registers that propagate from leaf level to the top Interrupt Controller.
  Developed comprehensive Block level Test Benches (TB) to validate functionality and performance.
  
• Statistics Module Integration:Led the integration of a Statistics module within the subsystem, identifying and organizing signals essential for maintaining packet statistics.
  Implemented statistics functionality to aid in debugging, tracking packet flow through various modules after injection via the Up-link ORAN Processor (ULOP). This involved monitoring Control plane packets as they formed User plane (U-plane) packets using Frequency Domain IQ samples (FDIQ).
  Developed a counter mechanism for capturing packet start (SOP) and end (EOP) signals, along with error flags. These statistics are stored in memory and are crucial for effective debugging.
  
• Collaboration with Digital Verification Team: Coordinated with the Digital Verification team to clarify design functionality, supporting configuration and driver sequencing requirements, and assisting with functional debugging efforts.
• Collaboration with Software and SQA Team: Partnered with the Software and Software Quality Assurance (SQA) teams to facilitate the effective bring-up of the subsystem for end-to-end test development. Provided guidance on sequencing for subsystem bring-up from top-level to leaf-level configurations.
• Support for Physical Design (PD) Team: Assisted the PD team in analyzing timing reports generated after the synthesis of the block. Conducted timing fixes where necessary and analyzed the optimized flip-flop list for correctness, providing fixes for incorrectly optimized flip-flops.

Project: Trace Unit Design for RISC-V Core

Role: Subsystem Designer Engineer

• Micro-Architecture Understanding: Conducted comprehensive analysis of the Trace Unit architecture for the RISC-V core, ensuring it met design requirements and performance benchmarks.
• RTL Development for Asynchronous FIFO: Developed RTL source code for an asynchronous FIFO tailored for the Trace Unit, focusing on efficient data handling and minimizing latency.
• SPI Slave Integration: Integrated SPI slave functionality into the Trace Unit for parallel off-chip transfer of trace packets, enhancing system throughput and communication efficiency.
• Static Code Verification: Performed extensive static code verification, including lint checks, CDC checks, and synthesis, to validate design correctness and adherence to industry standards.
• Basic Functionality Verification: Designed and implemented comprehensive Verilog test benches (TB) to ensure functional correctness and validate the operation of the Trace Unit.
• Collaboration with Verification Teams: Worked closely with the Digital Verification team to clarify design functionalities, support driver sequencing, and assist with functional debugging efforts.
• Documentation and Reporting: Maintained thorough documentation of design changes and verification results, providing insights for future design iterations and facilitating knowledge transfer.

Project: AXI-4 Lite Slave Design

Role: Subsystem Designer Engineer

• Memory Interface Requirements Analysis: Conducted a thorough analysis of memory interface requirements for AXI-4 Lite, ensuring alignment with system architecture and performance needs.
• RTL Implementation of AXI-4 Lite Slave: Designed and implemented an AXI-4 Lite slave interface using a Finite State Machine (FSM), supporting three types of burst transactions: fixed, incremental, and wrap.
• Integration with Memory: Managed the integration of the AXI-4 Lite slave with memory components, ensuring seamless data transfer and communication.
• Static Code Verification: Performed lint checks and synthesis on the AXI-4 Lite slave design to ensure adherence to coding standards and functional correctness.
• Collaboration and Documentation: Collaborated with cross-functional teams to clarify design specifications and documented all design and verification processes for future reference.