Ashwin Jose Kattikaran

Low Power RTL design:

• Hands-on experience in design and integration of ARM Q-channel device for peripheral IPs. Good knowledge of IP design guidelines.
• Developed In-band and out-band clock gating and deep-sleep wake-up strategies for IP.
• Supported design verification team in bringing up Q-channel test-benches and subsequent debug of waveforms using Synopsis Verdi.

SOC level CDC:

• Hands-on experience in set up of Questa CDC flow in SOC environment.
• Good knowledge of various synchronizer types and use cases.

Scripting and Automation:

• Automated IP to SOC CDC constraint porting using Python. Developed push-button script for CDC which automates manual hacks used in set-up.
• Developed TC shell scripts for database management and automated check-in of generated RTL files.

• Spyglass LINT: Hands-on experience in resolving AHB timing loops, inferred latches, un-driven input ports and port bit-width mismatches.
• RTL Integration: Wrapper RTL creation and integration of IPs in SOC. Good knowledge of ARM AHB, APB protocols.
• Scripting and Automation: Created RTL Munge scripts for automating port addition in generated RTL. Created XLS scrubbing scripts for PNR and synthesis constraints creation.