Summary
Overview
Work History
Education
Skills
Languages
Work Availability
Timeline
Generic
Ramyakrishna Devapati

Ramyakrishna Devapati

Bengaluru,Karanataka

Summary

Adept SOC Design Engineer with a proven track record at Intel Technology India, mastering physical design, IR EM, and low power design. Innovated the Cheetah R2G process, significantly enhancing efficiency and reliability. Skilled in EDA tools and Python scripting, demonstrating exceptional problem-solving abilities and a commitment to excellence in advanced technology nodes.

Overview

12
12
years of professional experience

Work History

SOC Design Engineer

Intel Technology India (P) Ltd
03.2018 - Current
  • Spearheaded IR and EM signoff closures, formulated IR EM strategies, and ensured IR EM closure for intricate full-chip and subsystem designs in advanced 7nm and 5nm technologies.
  • Innovated the Cheetah R2G process, enhancing IR EM and PD methodologies to improve efficiency and reliability.
  • Oversaw design planning and RTL to GDSII closure, with a focus on performance optimization and timing closure.
  • Executed physical design and signoff for various projects.

Senior Physical Design Engineer

Aricent
02.2017 - 03.2018
  • Led physical design and signoff for a subsystem consisting of 7 child blocks, overseeing the process from synthesis to GDSII closure
  • Successfully achieved optimal partitioning and timing closure for a 3.5 million-gate design, ensuring both manufacturability and performance

Physical Design Engineer

Infosys
02.2014 - 02.2017
  • Executed physical design and signoff for projects on cutting-edge 14nm and 10nm technologies, with a primary focus on achieving timing closure and optimizing performance.
  • Oversaw ECO and FV flows to enhance the overall accuracy and integrity of the design.

Systems Engineer

Rathna Biotek
Chittoor, Andhra Pradesh
07.2012 - 01.2014
  • Adaptable and proficient in learning new concepts quickly and efficiently.
  • Proven ability to learn quickly and adapt to new situations.
  • Assisted with day-to-day operations, working efficiently and productively with all team members.

Education

BTech - Electronics And Communication Engineering

JNTU-A
India
04.2012

Skills

  • Physical Design
  • IR EM
  • Low Power Design
  • Floorplanning
  • Static Timing Analysis
  • EDA Tool Expertise
  • AutoCAD
  • Python Scripting
  • Tcl and Tk Scripting

Languages

English
Professional Working
German
Elementary
Telugu
Native or Bilingual
Hindi
Native or Bilingual

Work Availability

monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
swipe to browse

Timeline

SOC Design Engineer

Intel Technology India (P) Ltd
03.2018 - Current

Senior Physical Design Engineer

Aricent
02.2017 - 03.2018

Physical Design Engineer

Infosys
02.2014 - 02.2017

Systems Engineer

Rathna Biotek
07.2012 - 01.2014

BTech - Electronics And Communication Engineering

JNTU-A

Similar Profiles

CREATE PROFILE
Ramyakrishna Devapati