Dimple Mondhe

𝐒𝐩𝐞𝐜𝐢𝐚𝐥𝐭𝐢𝐞𝐬: 𝐀𝐒𝐈𝐂 𝐏𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐃𝐞𝐬𝐢𝐠𝐧 𝐑𝐓𝐋𝟐𝐆𝐃𝐒𝐈𝐈

(Synthesis, Constraint Debug, Floorplanning, Congestion Reduction, Die-Size Reduction, Power routing/analysis and fixes, CTS, Routing, STA, ECO Fixes).

• Technologies: Across 𝐭𝐬𝐦𝐜𝐧7, 𝐭𝐬𝐦𝐜𝐧16, Intel10, Intel14 etc.
• Tools: DC Compiler, IC Compiler, IC Compiler-2, Primetime & Star-RC.
• Solid Experience in handling blocks/chip from Netlist2Tapeout
• Timely and qualitatively delivered complex Fabric and NOC blocks with multiple voltage designs across advanced process nodes.
• Performed Internal timing closure, FEV convergence, PDN and other quality checks.
• Worked closely with DA's and parallel teams across time zones.
• Experience in handling and developing complex flows.
• Resolve issues proactively and Value-add to the project on reducing cycle-time, efficient solutions.
• Implemented complex logic ECO's for various stepping, including metal-only.
• Strong leadership skills with ability to mentor Interns.

As an intern was engaged in multiple tasks.

• Worked in High velocity Product Group (HPG) with the Process Methodology Team.
• Involved in various UPF evaluation and analysis simulations using specific simulation tool and to calculate different parameters of device. With this tool, responsible in various other simulations like Monte Carlo and Most Probable Point (MPP). These simulations include analysis of different Std. library cells for different parameters like delay,Vt and leakage power.
• Involved in performing Monte Carlo simulations by using different grid length cells.
• In addition simulated different stages Ring Oscillators to compare delay variations.
• Performed various FEM simulations to evaluate UPF versions based on parameters like delay, switching energy.
• Experience with JMP (John's Macintosh Project) tool for analyzing data
• Involved in generating V/F curve for pre-silicon (used tool VF-Calculator)