Gurudatta Venkata Sai Prasanth Nandam
Summary
- Experience in block-level Physical Design - RTL to GDSII
- Experience in Static Timing Analysis and Timing Closure
- Experience in Physical verification - DRC/LVS, IR/EM, ECO cycle
- Experience in Full chip clock planning, FCT & FCFP
- Experience in Power FSDB's & SAIF
- Experience in TCL, Bash, Perl & Python scripting and automation
- Experience of working in 28nm, 32nm, 7nm & 5nm technology nodes
Overview
9
9
years of professional experience
Work History
Lead Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
02.2019 - Current
- Responsible for FSDB validation & integration to tile PNR for power optimization as power lead.
- Annotations, mappings & validation with automated scripts written for this project.
- Validating power intent and activity data consistency across simulation and synthesis stages to ensure power-aware design integrity.
- Helping Hyderabad PNR team on any PNR & flow Issues.
- Handling 2 resources for two parallel projects.
- 1 resource is new to clock gave complete KT on full chip clock activities.
- Logical connections planning for all clocks.
- Pushdown planning, Custom routing, Tmac simulations, Skew fixing & Automation.
Lead Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
01.2024 - 10.2025
- Responsible for handling 10 tiles (4 critical, 3 medium, 3 repeater tiles & PLL 2 blocks).
- PNR - responsible for PPA metrics closure across all milestones (LSA-LSD final PNR).
- Floorplan reviews, qor reviews across all stages & feedback to Tile owners.
- Eco execution and convergence on time.
- In sync with all stakeholders in issues resolving- RTL, FCFP, FCT, Constraints & flow teams.
- Worked in A0 & B0 versions of projects.
- Supported other chips in chiplet for PV closure with team of 10 members for on time BTO & MTO delivery.
- Executed all post project executions - final jiras, post tapeout issues validation, Disk reclaim & Backups for 60 tiles in project.
- Responsible for mentoring new engineers.
Lead Physical Design Engineer,Clock Engineer
Signoff Semiconductors Pvt. Ltd.
10.2022 - 12.2024
- Clock pushdown planning & review.
- Logical connections for all clocks.
- Tile level feedback implementations on pushdown cells.
- Skew, latency, uncertainty iterations & simulations.
- Manual DRC/EM/IR aware RDL routing with shielding's with Balanced net lengths.
- CES simulations for GC_GFXCLK skew, latency, tran, cap, fanout fixing and balancing across 20 levels.
- Guiding and supporting Hyderabad team juniors in AMD PNR flow, DTCO trails, ECO flows and support.
- Responsible for mentoring new engineers.
Senior Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
04.2022 - 08.2022
- Responsible for handling a block in Eco cycle.
- Responsible for lead Role with the team of 8 blocks.
- Worked on generating timing Eco's both manually and by scripting to implement it in the design.
- Converged a complex timing and routing critical design.
- Responsible for mentoring new engineers.
Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
03.2019 - 10.2019
- Responsible for ECO, Timing Closure and Physical Verification and IR/EM fixes for multiple tiles.
- Static timing analysis and Timing closure. DRC/ LVS fixing.
Associate Consultant
CapGemini Pvt. Ltd.
09.2016 - 02.2019
- Development and unit testing of Problem Report, Change Request and Enhancement Request.
- Created and documented conceptual and detail design of the application based on a description of the software requirement and specifications.
- Coordinated with Solution Architects for any design change in application or any patch fix.
- Responsible for IKEA OMS (Order Management System) & VMI (Vendor Managed Replenishment) Backend coding & operations.
- Coding of PL/SQL procedures, functions, and code reviews & checkins.
- Fully involved in the SDLC, used agile mode for the development.
- Automating the Routine tasks in Automation Anywhere and integration.
Education
SSC - undefined
Z.P.H.School
01.2010
Intermediate - undefined
Sri Chaitanya jr. college
01.2012
B.Tech - Electronics and Communications Engineering
KITS Markapur
01.2016
Skills
- VLSI Physical Design
- PnR flow
- Floorplanning
- Placement
- CTS
- Routing
- Synthesis
- ECO flow
- Static Timing Analysis
- Timing Closure
- DRC fixing
- Secondary metrics fixing
- Full Chip Clock planning
- Simulations
- Physical Verification
- Power optimization
- AI
- PD Agent
- GENIE
- PD GURU
- Advance prompting
- Entry level AI Generalist
- TCL
- Python
- Verilog
- Perl
- Automation
- IC Compiler II
- Fusion Compiler
- Innvos
- OpenRoad
- StarRC
- Verdi
- Prime Time
- Prime Closure
- Calibre
- TSMC 28nm
- TSMC 32nm
- TSMC 7nm
- TSMC 5nm
- TSMC 2nm
Languages
TCL
Python
Verilog
Perl
Automation
Personal Information
- Total Experience: 9 years
- Title: Lead Physical Design Engineer
Personal Qualifications
B.Tech, Electronics and Communications Engineering, JNTUK University
Primary Skills
- 7+ years experience in VLSI Physical Design
- PnR flow - Floorplanning, Placement, CTS, Routing
- Synthesis
- ECO flow - Static Timing Analysis, Timing Closure, complex DRC & Secondary metrics fixing
- Full Chip Clock planning & Simulations
- Physical Verification
- Power optimization FSDB, SAIF
- AI enthusiast, PD Agent, GENIE, PD GURU, Advance prompting, Entry level AI Generalist
Eda Tools
IC Compiler II, Fusion Compiler, Innovus, OpenRoad, StarRC, Verdi, Prime Time, Prime Closure, Calibre
Tech Nodes Experience
- TSMC 28nm
- TSMC 32nm
- TSMC 7nm
- TSMC 5nm
- TSMC 2nm
Timeline
Lead Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
01.2024 - 10.2025
Lead Physical Design Engineer,Clock Engineer
Signoff Semiconductors Pvt. Ltd.
10.2022 - 12.2024
Senior Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
04.2022 - 08.2022
Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
03.2019 - 10.2019
Lead Physical Design Engineer
Signoff Semiconductors Pvt. Ltd.
02.2019 - Current
Associate Consultant
CapGemini Pvt. Ltd.
09.2016 - 02.2019
SSC - undefined
Z.P.H.School
Intermediate - undefined
Sri Chaitanya jr. college
B.Tech - Electronics and Communications Engineering
KITS Markapur