Manish Kumar Roy

Aspiring VLSI engineer seeking opportunities to gain practical knowledge, enhance skills and contribute value to the organization and the industry.

• Design and Analysis of MAC Unit using Verilog
• Design of 1 X 3 Router using Verilog
• Simulation of LEACH and PEGASIS protocols for WSNs.

• 3 Days Hands on training on "Cadence EDA tool for Chip Design (Analog RF and Digital Flows)"

• English
• Hindi
• Bengali
• Assamese

Cadet In NCC (2012-2015)

SPORTS- Cricket,Badminton

Poetry, Singing, Guitar