HARI PRAKASH REDDY B
Guntur
Summary
Physical Design Engineer with 2+ years of working experience and with good scripting skills, Worked in Technical Roles for one successful Tape out.
Overview
2
2
years of professional experience
Work History
Physical Design Engineer
Soctronics Technologies Pvt Limited
Guntur
08.2022 - Current
- Worked with different stages of PnR for high performance core for 5nm and interacted with Physical Verification and IREM teams to clear LVS, IR Drop and DRC's
- Executed ECO's for 2 blocks with instance count of 1M to clear all the design and timing violations includes data transition, SI, and DRC's
- Analyzed issues of timing and routing critical blocks with clock frequency of 1.35GHz and cleared timing issues in the design improve the QoR by 30% in PnR
- Implemented Bus plan repeater implementation in channel block to improve resistance of bus to SI effects
- Guided clock building in CTS to minimize clock latency, reduced median latency by 20%
- Wrote scripts in TCL and Python to extract different info such as net length and delay fanout from design and existing reports to make ECO work better and easy
- Good Understanding in different place and route flows (MV, DFP, VA)
- Addressed VSI (Low Power verification) issues, Formality issues and UPF related issues
- Guided Trainee engineers in effectively resolving technical issues
- Cleaned DRC's and LVS issues in TSMC 5nm node
- Extensive understanding of RTL2GDSII Flow
Physical Design Engineer Trainee
VEDA IIT
Guntur
02.2022 - 08.2022
- Done PnR for 28nm full chip design with instance count of 0.5M.
- Explored and learned different scripting languages and used them to optimize the design
- Extensive understanding of physical design fundamentals, Digital circuit design, and fabrication process.
Education
Bachelor of Technology [B.Tech] [Electronics & Communication] -
GMR Institute of Technology
05.2022
Skills
- Physical Design
- Floor-planning
- STA
- Place and Route (PNR)
- IREM
- Primetime
- ICC2
- Fusion Compiler
- Timing Closure
- Digital circuit design
- Placement Optimization
- Semiconductor Physics
- Multi Voltage Areas
- Physical extraction
- Power Saving Methodologies
- DRC, and LVS (schematic to layout verification)
- AOCV, POCV
- Python
- TCL
- C Shell, Unix, Windows
- VLSI
- Verilog
- Synthesis
- Analog
- CMOS Technology, and FinFET
- C/C
- Programming Concepts - OOPS Through Python and TCL,
- Multi Processing and Multithreading
Accomplishments
- Holder of GMRIT Merit Scholarship for consistently in the top 10% at college
- Cleared GATE 2021 with an ALL INDIA 2567
- Awarded in the top 3 for Autonomous bot design at STEPCONE 2020.
- Hosted a Guest Lecture in Govt school about 'Importance of Education'
Timeline
Physical Design Engineer
Soctronics Technologies Pvt Limited
08.2022 - Current
Physical Design Engineer Trainee
VEDA IIT
02.2022 - 08.2022
Bachelor of Technology [B.Tech] [Electronics & Communication] -
GMR Institute of Technology
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