NAKUL SENGAL

Detail-oriented intern with a strong foundation in ASIC design flow, Linux environments, and shell scripting. Eager to contribute problem-solving skills to enhance circuit design and simulation processes. Committed to digital electronics and Verilog HDL, enthusiastic about utilizing skills in vibrant environments.

• VLSI Digital Design - Chip Design and Verilog Programming From INFOSYS
• VLSI SoC Design using Verilog HDL -Maven Silicon

• GATE 2025 Qualifier with Gate Score 311

• Traffic Light Controller - The Project aims to design a verilog HDL based traffic light controller that sequence three traffic light to manage intersection traffic flow.
• Finite State Machine - It involves designing a verilog HDL based FSM circuit that transition between state in response to external inputs based on predefined condition.
• FIFO - The project involves designing a verilog HDL based FIFO buffer with configurable depth and width for versatile data storage and transfer in digital system.